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Details, datasheet, quote on part number:X25401S
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Datasheet text preview:
APPLICATION NOTE
AVAILABLE
X25401 256 Bit
AN56
X25401
SPI Serial AUTOSTORETM NOVRAM
16 x 16 Bit
FEATURES
DESCRIPTION
The Xicor X25401 is a serial 256 bit NOVRAM featuring a static RAM configured 16 x 16, overlaid bit-by-bit with a nonvolatile E2PROM array. The X25401 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The Xicor NOVRAM design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. A store operation (RAM data to E2PROM) is completed in 5ms or less and a recall operation (E2PROM data to RAM) is completed in 2µs or less. The X25401 also includes the AUTOSTORE feature, a user selectable feature that automatically performs a store operation when VCC falls below a preset threshold. Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM and a minimum 1,000,000 store operations. Inherent data retention is specified to be greater than 100 years.
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1MHz Clock Rate AUTOSTORETM NOVRAM --Automatically Performs a Store Operation Upon Loss of VCC Single 5 Volt Supply Ideal for use with Single Chip Microcomputers --Minimum I/O Interface --SPI Mode (0,0 & 1,1) Serial Port Compatible --Easily Interfaced to Microcontroller Ports Software and Hardware Control of Nonvolatile Functions Auto Recall on Power-Up TTL and CMOS Compatible Low Power Dissipation --Active Current: 10mA --Standby Current: 50µA 8-Lead PDIP and 8-Lead SOIC Packages High Reliability --Store Cycles: 1,000,000 --Data Retention: 100 Years
FUNCTIONAL DIAGRAM
NONVOLATILE 2 E PROM
R E
ROW DECODE
STATIC RAM 256-BIT
EC
AL L
ST O
CONTROL LOGIC
R
RECALL (6) AS (7)
CS (1) SI (3) SCK (2)
INSTRUCTION REGISTER
COLUMN DECODE
SO (4)
INSTRUCTION DECODE
4-BIT COUNTER
2051 FHD F01
AUTOSTORETM NOVRAM is a trademark of Xicor, Inc. COPS is a trademark of National Semiconductor Corp.
© Xicor, Inc. 1992, 1995, 1996 Patents Pending 2051-1.5 8/1/97 T0/C0/D2 SH
1
Characteristics subject to change without notice
X25401
PIN DESCRIPTIONS Chip Select (CS) The Chip Select input must be LOW to enable all read/ write operations. CS must remain LOW following a Read or Write command until the data transfer is complete. CS HIGH places the X25401 in the low power standby mode and resets the instruction register. Therefore, CS must be brought HIGH after the completion of an operation in order to reset the instruction register in preparation for the next command. Serial Clock (SCK) The Serial Clock input is used to clock all data into and out of the device. Serial Data In (SI) SI is the serial data input. Serial Data Out (SO) SO is the serial data output. It is in the high impedance state except during data output cycles in response to a READ instruction. AUTOSTORE Output (AS) AS is an open drain output which, when asserted indicates VCC has fallen below the AUTOSTORE threshold (VASTH). AS may be wire-ORed with multiple open drain outputs and used as an interrupt input to a microcontroller or as an input to a low power reset circuit. RECALL RECALL LOW will initiate an internal transfer of data from E2PROM to the RAM array. PIN NAMES Symbol CS SCK SI SO RECALL AS VCC VSS Description Chip Enable Serial Clock Serial Data In Serial Data Out Recall Input AUTOSTORE Output +5V Ground
2051 PGM T01
2051 FHD F02
PIN CONFIGURATION
DIP/SOIC CS SCK SI SO 1 2 3 4 X25401 8 7 6 5 VCC AS RECALL VSS
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X25401
DEVICE OPERATION The X25401 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire data transfer operation. Table 1 contains a list of the instructions and their operation codes. The most significant bit (MSB) of all instructions is a logic one (HIGH), bits 6 through 3 are either RAM address bits (A) or don't cares (X) and bits 2 through 0 are the operation codes. The X25401 requires the instruction to be shifted in with the MSB first. After CS is LOW, the X25401 will not begin to interpret the data stream until a logic "1" has been shifted in on SI. Therefore, CS may be brought LOW with SCK running and SI LOW. SI must then go HIGH to indicate the start condition of an instruction before the X25401 will begin any action. In addition, the SCK clock is totally static. The user can completely stop the clock and data shifting will be stopped. Restarting the clock will resume shifting of data. RCL and RECALL Either a software RCL instruction or a LOW on the RECALL input will initiate a transfer of E2PROM data into RAM. This software or hardware recall operation sets an internal "previous recall" latch. This latch is reset upon power-up and must be intentionally set by the user to enable any write or store operations. Although a recall operation is performed upon power-up, the previous recall latch is not set by this operation. WRDS and WREN Internally the X25401 contains a "write enable" latch. This latch must be set for either writes to the RAM or store operations to the E2PROM. The WREN instruction sets the latch and the WRDS instruction resets the latch, disabling both RAM writes and E2PROM stores, effectively protecting the nonvolatile data from corruption. The write enable latch is automatically reset on power-up. STO The software STO instruction will initiate a transfer of data from RAM to E2PROM. In order to safeguard against unwanted store operations, the following conditions must be true: · STO instruction issued. · The internal "write enable" latch must be set (WREN instruction issued). · The "previous recall" latch must be set (either a software or hardware recall operation). Once the store cycle is initiated, all other device functions are inhibited. Upon completion of the store cycle, the write enable latch is reset. Refer to Figure 4 for a state diagram description of enabling/disabling conditions for store operations.
TABLE 1. INSTRUCTION SET Instruction WRDS (Figure 3) STO (Figure 3) ENAS WRITE (Figure 2) WREN (Figure 3) RCL (Figure 3) READ (Figure 1)
X = Don't Care A = Address
Format, I2 I1 I0 1XXXX000 1XXXX001 1XXXX010 1AAAA011 1XXXX100 1XXXX101 1AAAA11X
Operation Reset Write Enable Latch (Disables Writes and Stores) Store RAM Data in E2PROM Enable AUTOSTORE Feature Write Data into RAM Address AAAA Set Write Enable Latch (Enables Writes and Stores) Recall E2PROM Data into RAM Read Data from RAM Address AAAA
2051 PGM T11
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