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Details, datasheet, quote on part number:X25640SM
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Datasheet text preview:
APPLICATION NOTES
AVAILABLE
X25640 64K
AN19 · AN38 · AN41 · AN61
X25640
DESCRIPTION
8K x 8 Bit
Advanced SPI Serial E2PROM With Block LockTM Protection
FEATURES
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1MHz Clock Rate Low Power CMOS --200µA Standby Current --5mA Active Current 5 Volt Power Supply SPI Modes (0,0 & 1,1) 8K X 8 Bits --32 Byte Page Mode Block Lock Protection --Protect 1/4, 1/2 or all of E2PROM Array Built-in Inadvertent Write Protection --Power-Up/Power-Down protection circuitry --Write Enable Latch --Write Protect Pin Self-Timed Write Cycle --5ms Write Cycle Time (Typical) High Reliability --Endurance: 100,000 cycles --Data Retention: 100 Years --ESD protection: 2000V on all pins 8-Lead PDlP Package 14-Lead SOIC Package
The X25640 is a CMOS 65,536-bit serial E2PROM, internally organized as 8K x 8. The X25640 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25640 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25640 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25640 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25640 utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
STATUS REGISTER WRITE PROTECT LOGIC X DECODE LOGIC 64 64 X 256 SO SI SCK CS HOLD COMMAND DECODE AND CONTROL LOGIC 64 64 X 256 8K BYTE ARRAY
128 128 X 256
WP
WRITE CONTROL AND TIMING LOGIC 32 8 Y DECODE DATA REGISTER
3089 ILL F01
Direct WriteTM and Block LockTM Protection is a trademark of Xicor, Inc. ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 3089-1.8 6/17/96 T4/C4/D1 NS
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Characteristics subject to change without notice
X25640
PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25640 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25640 will be in the standby power mode. CS LOW enables the X25640, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW and the nonvolatile bit WPEN is high, nonvolatile writes to the X25640 status register are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25640 status register. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. The WP pin function is blocked when the WPEN bit in the status register is LOW. This allows the user to install the X25640 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set "1". Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while
NC NC CS SO WP VSS NC CS SO WP VSS 1 2 3 4
SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. PIN CONFIGURATION
8-LEAD DIP 8 VCC HOLD SCK SI
X25640
7 6 5
14-LEAD SOIC 1 2 3 4 5 6 7 14 13 12 NC NC VCC HOLD SCK SI NC
3089 ILL F02.3
X25640 11
10 9 8
PIN NAMES Symbol CS SO SI SCK WP VSS VCC HOLD NC Description Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Hold Input No Connect
3089 PGM T01
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X25640
PRINCIPLES OF OPERATION The X25640 is a 8K x 8 designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families. The X25640 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and the HOLD and WP inputs must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the X25640 into a "PAUSE" condition. After releasing HOLD, the X25640 will resume operation from the point when HOLD was first asserted. Write Enable Latch The X25640 contains a "write enable" latch. This latch must be SET before a write operation will be completed internally. The WREN instruction will set the latch and the WRDI instruction will reset the latch. This latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle. E2PROM Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: 7 6 WPEN X 5 X 4 X 3 BP1 2 BP0 1 WEL 0 WIP
3089 PGM T02
WPEN, BP0 and BP1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set by other operations. The Write-In-Process (WIP) bit indicates whether the X25640 is busy with a write operation. When set to a "1", a write is in progress, when set to a "0", no write is in progress. During a write, all other bits are set to "1". The Write Enable Latch (WEL) bit indicates the status of the "write enable" latch. When set to a "1", the latch is set, when set to a "0", the latch is reset. The Block Protect (BP0 and BP1) bits are nonvolatile and allow the user to select one of four levels of protection. The X25640 is divided into four 16384-bit segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated below. Status Register Bits BP1 BP0 0 0 1 1 0 1 0 1 Array Addresses Protected None $1800$1FFF $1000$1FFF $0000$1FFF
3834 PGM T03
Table 1. Instruction Set Instruction Name WREN WRDI RDSR WRSR READ WRITE Instruction Format* 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 Operation Set the Write Enable Latch (Enable Write Operations) Reset the Write Enable Latch (Disable Write Operations) Read Status Register Write Status Register Read Data from Memory Array beginning at selected address Write Data to Memory Array beginning at Selected Address (1 to 32 Bytes)
3089 PGM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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