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Details, datasheet, quote on part number:X25F128SE-5
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Datasheet text preview:
APPLICATION NOTE A V A I LABLE
AN61 · AN75 X25F128 · AN77 · AN79 · AN82
X25F128
FEATURES
· 1MHz Clock Rate · SPI Serial Interface · 16K X 8 Bits -- 32 Byte Small Sector Program Mode · Low Power CMOS -- <1µA Standby Current -- <5mA Active Current · 1.8V 3.6V or 5V "Univolt" Read and Program Power Supply Versions · Block Lock Protection -- Protect 1/4, 1/2 or all of E2PROM Array · Built-in Inadvertent Program Protection -- Power-Up/Power-Down protection circuitry -- Program Enable Latch -- Program Protect Pin · Self-Timed Program Cycle -- 5ms Program Cycle Time (Maximum) · High Reliability -- Endurance: 100,000 cycles per byte -- Data Retention: 100 Years -- ESD protection: 2000V on all pins · 8-Lead PDlP Package · 16-Lead 150 mil SOIC Package FUNCTIONAL DIAGRAM
DATA REGISTER SI SECTOR DECODE LOGIC SO COMMAND DECODE AND CONTROL LOGIC 32 X DECODE LOGIC 8
16K x 8 Bits
SerialFlashTM Memory With Block LockTM Protection
DESCRIPTION
The X25F128 is a 131,072-bit CMOS SerialFlash memor y, internally organized 16K X 8. It features a "Univolt" Program and Read voltage, Serial Peripheral Interface (SPI), and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK), plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25F128 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25F128 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The PP input can be used as a hardwire input to the X25F128 disabling all program attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2, or all of the memory. The X25F128 utilizes Xicor's proprietary flash cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
SCK
MEMORY ARRAY
CS HOLD STATUS REGISTER
PP
PROGRAMMING CONTROL LOGIC
HIGH VOLTAGE CONTROL
6829 ILL F01.1
SerialFlashTM and Block LockTM Protection are trademarks of Xicor, Inc. © Xicor, Inc. 1995, 1996 Patents Pending 6829-1.9 4/7/97 T3/C0/D0 SH
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Characteristics subject to change without notice
X25F128
PIN DESCRIPTIONS Serial Output (SO) SO is a push-pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25F128 is deselected and the SO output pin is at high impedance and unless an internal program operation is underway the X25F128 will be in the standby power mode. CS LOW enables the X25F128, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Program Protect (PP) When PP is LOW and the nonvolatile bit PPEN is "1", nonvolatile programming of the X25F128 status register is disabled, but the part otherwise functions normally. When PP is held HIGH, all functions, including nonvolatile programming operate normally. PP going LOW while CS is still LOW will interrupt programming of the X25F128 status register. If the internal program cycle has already been initiated, PP going LOW will have no effect on programming. The PP pin function is blocked when the PPEN bit in the status register is "0". This allows the user to install the X25F128 into a system with PP pin grounded and still be able to program the status register. The PP pin functions will be enabled when the PPEN bit is set "0". Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. PIN CONFIGURATION
8-LEAD DIP CS SO PP VSS 1 2 3 4 X25F128 8 7 6 5 VCC HOLD SCK SI
16-LEAD SOIC CS SO NC NC NC NC PP VSS 1 2 3 4 5 6 7 8 X25F128 16 15 14 13 12 11 10 9 VCC HOLD NC NC NC NC SCK SI
6829 ILL F02.1
PIN NAMES SYMBOL CS SO SI SCK PP VSS VCC HOLD NC DESCRIPTION Chip Select Input Serial Output Serial Input Serial Clock Input Program Protect Input Ground Supply Voltage Hold Input No Connect
6829 PGM T01
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X25F128
PRINCIPLES OF OPERATION The X25F128 is a SerialFlash Memory designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families. The X25F128 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and the HOLD and PP inputs must be HIGH during the entire operation. The PP input is "Don't Care" if PPEN is set "0". Table 1 contains a list of the instructions and their operation codes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the X25F128 into a "PAUSE" condition. After releasing HOLD, the X25F128 will resume operation from the point when HOLD was first asserted. Program Enable Latch The X25F128 contains a program enable latch. This latch must be SET before a program operation will be completed internally. The PREN instruction will set the latch and the PRDI instruction will reset the latch. This latch is automatically reset on power-up and after the completion of a sector program or status register write cycle. Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a program cycle. The status register is formatted as follows: 7 PPEN 6 X 5 X 4 X 3 BL1 2 BL0 1 PEL 0 PIP
6829 PGM T02
PPEN, BL0, and BL1 are set by the PRSR instruction. PEL and PIP are "read-only" and automatically set by other operations. T h e Programming-In-Process (PIP) bit indicates whether the X25F128 is busy with a program operation. When set to a "1" programming is in progress, when set to a "0" no programming is in progress. During programming, all other bits are set to "1". The Program Enable Latch (PEL) bit indicates the status of the program enable latch. When set to a "1" the latch is set; when set to a "0" the latch is reset. The Block Lock (BL0 and BL1) bits are nonvolatile and allow the user to select one of four levels of protection. The X25F128 array is divided into four equal segments. One, two, or all four of the segments may be locked. That is, the user may read the segments, but will be unable to alter (program) data within the selected segments. The partitioning is controlled as illustrated below. Status Register Bits BL1 BL0 0 0 1 1 0 1 0 1 Array Addresses Locked None upper fourth upper half All
6829 PGM T03.1
Program-Protect Enable T h e Program-Protect-Enable bit (PPEN) in the X25F128 status register acts as an enable bit for the PP pin.
Table 1. Instruction Set Instruction Name PREN PRDI RDSR PRSR READ PROGRAM Instruction Format* 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 Operation Set the Program Enable Latch (Enable Program Operations) Reset the Program Enable Latch (Disable Program Operations) Read Status Register Program Status Register Read from Memory Array beginning at Selected Address Program Memory Array beginning at Selected Address (32 Bytes)
6829 PGM T04.1
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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