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Details, datasheet, quote on part number:X28C64K
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Datasheet text preview:
X28C64 64K
X28C64
5 Volt, Byte Alterable E2PROM
DESCRIPTION
8K x 8 Bit
FEATURES
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150ns Access Time Simple Byte and Page Write --Single 5V Supply --No External High Voltages or VPP Control Circuits --Self-Timed --No Erase Before Write --No Complex Programming Algorithms --No Overerase Problem Low Power CMOS --60mA Active Current Max. --200µA Standby Current Max. Fast Write Cycle Times --64 Byte Page Write Operation --Byte or Page Write Cycle: 5ms Typical --Complete Memory Rewrite: 0.625 sec. Typical --Effective Byte Write Cycle Time: 78µs Typical Software Data Protection End of Write Detection --DATA Polling --Toggle Bit High Reliability --Endurance: 100,000 Cycles --Data Retention: 100 Years JEDEC Approved Byte-Wide Pinout
The X28C64 is an 8K x 8 E2PROM, fabricated with Xicor's proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the X28C64 is a 5V only device. The X28C64 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs. The X28C64 supports a 64-byte page write operation, effectively providing a 78µs/byte write cycle and enabling the entire memory to be typically written in 0.625 seconds. The X28C64 also features DATA and Toggle Bit Polling, a system software support scheme used to indicate the early completion of a write cycle. In addition, the X28C64 includes a user-optional software data protection mode that further enhances Xicor's hardware write protect capability. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
PIN CONFIGURATION
PLASTIC DIP CERDIP FLAT PACK SOIC
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X28C64 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/04 I/O3
A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 X28C64
LCC PLCC
VCC A12 WE NC NC NC A7
TSOP
A2 A1 A0 I/O0 I/O1 I/O2 NC VSS NC I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A3 A4 A5 A6 A7 A12 NC NC VCC NC WE NC A8 A9 A11 OE
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3
2
1 32 31 30 29 28 27 26 25 24 23 22 A8 A9 A11 NC OE A10 CE I/O7 I/O6
X28C64
21 13 14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
3853 ILL F23.1
3853 FHD F03
3853 FHD F02
© Xicor, Inc. 1991, 1995 Patents Pending 3853-2.7 4/2/96 T0/C3/D2 NS
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Characteristics subject to change without notice
X28C64
PIN DESCRIPTIONS Addresses (A0A12) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. PIN NAMES Symbol A0A12 I/O0I/O7 WE CE OE VCC VSS NC FUNCTIONAL DIAGRAM
65,536-BIT E2PROM ARRAY
I/O1 I/O2 I/O3 I/O5 I/O6 12 13 15 17 18 I/O0 A0 11 10 VSS I/O4 I/O7 14 16 19 CE 20 X28C64 OE 22 A10 21 A11 23 A8 25 NC 26
Data In/Data Out (I/O0I/O7) Data is written to or read from the X28C64 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C64. PIN CONFIGURATION
PGA
Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
3853 PGM T01
9
A1 A3 A5
8
A2 A4 A12
7
6
5
2
VCC A9 28 24 NC 1 WE 27
4
A6
3
A7
BOTTOM VIEW
3853 FHD F04
X BUFFERS LATCHES AND DECODER A0A12 ADDRESS INPUTS Y BUFFERS LATCHES AND DECODER
I/O BUFFERS AND LATCHES
I/O0I/O7 DATA INPUTS/OUTPUTS CE OE WE VCC VSS
3853 FHD F01
CONTROL LOGIC AND TIMING
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X28C64
DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C64 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation The page write feature of the X28C64 allows the entire memory to be written in 0.625 seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the X28C64 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A6 through A12) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs. Write Operation Status Bits The X28C64 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
RESERVED TOGGLE BIT DATA POLLING
3853 FHD F11
DATA Polling (I/O7) The X28C64 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C64, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the X28C64 is in the protected state and an illegal write operation is attempted DATA Polling will not operate. Toggle Bit (I/O6) The X28C64 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
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