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Details, datasheet, quote on part number:X40235S16I-B
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| Part: | X40235S16I-B |
| Category: | Power Management => Supervisory Circuits => Microprocessor Supervisors |
| Description: | Integrated System Management Ictriple Voltage Monitors, Por, 2 Kbit EePROM Memory, And Single DCP |
| Company: | Xicor, Inc. |
| Datasheet: | Download X40235S16I-B datasheet File size : 221 kB |
| Request For quote: | Find where to buy X40235S16I-B
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Datasheet text preview:
Preliminary Information
X4023x
Integrated System Management IC
Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP
FEATURES · Triple Voltage Monitors -- User Programmable Threshold Voltage -- Power On Reset (POR) Circuitry -- Software Selectable Reset timeout -- Manual Reset Input · 2-Wire industry standard Serial Interface · 2 kbit EEPROM with Write Protect & Block LockTM · Digitally Controlled Potentiometers (DCP) X4023X Family Selector Guide
X= 256 tap 100 tap 64 Tap 1 3 5 7 9 1 1 1 1 1 1 1
DESCRIPTION The X4023x family of Integrated System Management ICs combine CPU Supervisor functions (VCC Power On Reset (POR) circuitry, two additional programmable voltage monitor inputs with software and hardware indicators), integrated EEPROM with Block LockTM protection and one or two Xicor Digitally Controlled Potentiometers (XDCP). All functions of the X4023x are accessed by an industry standard 2-Wire serial interface. APPLICATIONS The DCP of the X4023x may be utilized to software control analog voltages for: LCD contrast, LCD purity, or Backlight control. Power Supply settings such as PWM frequency, Voltage Trimming or Margining (temperature offset control). Reference voltage setting (e.g. DDR-SDRAM SSTL-2) The 2 kbit integrated EEPROM may be used to store ID, manufacturer data, maintenance data and module definition data. The programmable POR circuit insures VCC is stable before RESET is removed and protects against brownouts and power failures. The programmable voltage monitors have on-chip independent reference alarm levels. With separate outputs, the voltage monitors can be used for power on sequencing.
--Total Resistance 256 Tap = 100 k, 100 Tap or 64 Tap = 10 k --Nonvolatile wiper position -- Write Protect Function · Single Supply Operation --2.7 V to 5.5 V · 16 Pin SOIC (300) package -- SOIC BLOCK DIAGRAM
8 WP
RH PROTECT LOGIC
WIPER COUNTER REGISTER
RW
256 Tap DCP
SDA
DATA REGISTER COMMAND DECODE & CONTROL LOGIC THRESHOLD RESET LOGIC
CR REGISTER 4
8 - BIT NONVOLATILE MEMORY
SCL
2 kbit EEPROM ARRAY
WIPER COUNTER REGISTER
RH RW Optional 64 or 100 Tap DCP
Manual Reset (MR)
2
+
8 - BIT NONVOLATILE MEMORY
V3MON VTRIP3 V2MON VTRIP2 VCC VSS VTRIP1
V3FAIL
+
V2FAIL
+
POWER ON / LOW VOLTAGE RESET GENERATION
RESET
©2000 Xicor Inc., Patents Pending (VTRIP1,2,3 are user programmable)
REV 1.0.4 7/12/01
www.xicor.com
Characteristics subject to change without notice.
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X4023x Preliminary Information
PIN CONFIGURATION
SINGLE XDCP X40231 16 Pin SOIC NC NC V3MON V3FAIL MR WP SCL SDA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET V2FAIL V2MON RW0 RH0 NC VSS NC NC V3MON V3FAIL MR WP SCL SDA X40233 16 Pin SOIC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET V2FAIL V2MON NC RH1 RW1 VSS RH2 RW2 V3MON V3FAIL MR WP SCL SDA X40235 16 Pin SOIC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET V2FAIL V2MON NC NC NC VSS
DUAL XDCP
X40237 16 Pin SOIC
X40239 16 Pin SOIC VCC RESET V2FAIL V2MON RW0 RH0 NC VSS RH2 RW2 V3MON V3FAIL MR WP SCL SDA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET V2FAIL V2MON NC RH1 RW1 VSS
RH2 RW2 V3MON V3FAIL MR WP SCL SDA
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
REV 1.0.4 7/12/01
www.xicor.com
Characteristics subject to change without notice.
2 of 39
X4023x Preliminary Information
X40231 PIN ASSIGNMENT
SOIC 1 2 3 Name NC NC V3MON No Connect No Connect V3MON Voltage Monitor Input. V3MON i s the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than the VTRIP3 threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to VSS when not used. V3MON RESET Output. This open drain output makes a transition to a HIGH level when V3MON is greater than VTRIP3 and goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires the use of an external "pull-up" resistor. Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (VCC RESET Output pin). RESET will remain HIGH for time tPURST after MR has returned to it's normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of an external "pull-down" resistor. Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile "write" operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no "write" (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal "pull-down" resistor, thus if left floating the write protection feature is disabled. Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. Ground. No Connect Connection to end of resistor array for (the 64 Tap) DCP. Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP. V2MON Voltage Monitor Input. V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than the VTRIP2 threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to VSS when not used. V2MON RESET Output. This open drain output makes a transition to a HIGH level when V2MON is greater than VTRIP2, and goes LOW when V2MON is less than VTRIP2. There is no power up reset delay circuitry on this pin. The V2FAIL pin requires the use of an external "pull-up" resistor. VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever VCC falls below VTRIP1. RESET becomes active on power up and remains active for a time tPURST after the power supply stabilizes (tPURST can be changed by varying the PUP0 and PUP1 bits of the internal control register). The RESET pin requires the use of an external "pull-up" resistor. The RESET pin can be forced active (HIGH) using the manual reset (MR) input pin. Supply Voltage. Function
4
V3FAIL
5
MR
6
WP
7
SCL
8 9 10 11 12
SDA VSS NC RH0 RW0 V2MON
13
14
V2FAIL
15
RESET
16
VCC
REV 1.0.4 7/12/01
www.xicor.com
Characteristics subject to change without notice.
3 of 39
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