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Details, datasheet, quote on part number:X4045S8I2.7A
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Datasheet text preview:
4K
X4043/45
CPU Supervisor with 4Kbit EEPROM
512 x 8 Bit
FEATURES · Selectable watchdog timer · Low VCC detection and reset assertion -- Five standard reset threshold voltages -- Adjust low VCC reset threshold voltage using special programming sequence -- Reset signal valid to VCC = 1V · Low power CMOS -- <20µA max standby current, watchdog on -- <1µA standby current, watchdog OFF -- 3mA active current · 4Kbits of EEPROM -- 16-byte page write mode -- Self-timed write cycle -- 5ms write cycle time (typical) · Built-in inadvertent write protection -- Power-up/power-down protection circuitry -- Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes of EEPROM array with Block LockTM protection · 400kHz 2-wire interface · 2.7V to 5.5V power supply operation · Available packages -- 8-lead SOIC -- 8-lead MSOP -- 8-lead PDIP
DESCRIPTION The X4043/45 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.
BLOCK DIAGRAM
Watchdog Transition Detector WP SDA Data Register Command Decode & Control Logic VCC Threshold Reset logic Block Lock Control Protect Logic Status Register EEPROM Array 2Kbits 1Kb 1Kb RESET (X4043) RESET (X4045) Reset & Watchdog Timebase Watchdog Timer Reset
SCL
VCC VTRIP
+ -
Power on and Low Voltage Reset Generation
REV 1.1.17 9/14/01
www.xicor.com
Characteristics subject to change without notice.
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X4043/45
The memory portion of the device is a CMOS Serial EEPROM array with Xicor's block lock protection. The array is internally organized as x 8. The device features an 2-wire interface and software protocol allowing operation on an I2C bus. The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP, PDIP NC NC RESET VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
Pin (SOIC/MSOP/DIP)
1 2 3
Name
NC NC RESET/ RESET No internal connections No internal connections
Function
Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below VTRIP. It will remain active until VCC rises above the VTRIP for tPURST. RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. RESET/RESET goes active on power up and remains active for 250ms after the power supply stabilizes. RESET is an active high open drain output. An external pull up resistor is required on the RESET/RESET pin. Ground Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Serial Clock. The Serial Clock input controls the serial bus timing for data input and output. Write Protect. WP HIGH prevents writes to any location in the device (including the control register). Connect WP pin to VSS when it is not used. Supply Voltage
4 5
VSS SDA
6 7 8
SCL WP VCC
REV 1.1.17 9/14/01
www.xicor.com
Characteristics subject to change without notice.
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X4043/45
PRINCIPLES OF OPERATION Power On Reset Application of power to the X4043/45 activates a Power On Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. It prevents the system microprocessor from starting to operate with insufficient voltage. It prevents the processor from operating prior to stabilization of the oscillator. It allows time for an FPGA to download its configuration prior to initialization of the circuit. When VCC exceeds the device VTRIP threshold value for 200ms (nominal) the circuit releases RESET/ RESET allowing the system to begin operation. Low Voltage Monitoring During operation, the X4043/45 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. A standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the (RESET/RESET) signal going active. A minimum sequence to reset the watchdog timer requires four microprocessor intructions namely, a Start, Clock Low, Clock High and Stop. (See Page 18) The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be "locked" by tying the WP pin HIGH. Figure 1. Watchdog Restart
.6µs SCL 1.3µs
SDA Star t WDT Reset Stop
EEPROM Inadvertent Write Protection When RESET/RESET goes active as a result of a low voltage condition (VCC < VTRIP), any in-progress communications are terminated. While VCC < VTRIP, no new communications are allowed and no nonvolatile write operation can start. Nonvolatile writes in-progress when RESET/RESET goes active are allowed to finish. Additional protection mechanisms are provided with memory block lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. VTRIP Programming The X4043/45 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X4043/45 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal.
Figure 2. Set VTRIP Level Sequence (VCC = desired VTRIP values WEL bit set)
WP VP = 15-18V
01234567 SCL
01234567
01234567
SDA A0h 01h 00h
REV 1.1.17 9/14/01
www.xicor.com
Characteristics subject to change without notice.
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