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Details, datasheet, quote on part number:X40626V14I4.5A
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Datasheet text preview:
Preliminary Information 64K
X40626
Dual Voltage CPU Supervisor with 64K Serial EEPROM
DESCRIPTION
8K x 8 Bit
FEATURES ˇ Dual voltage monitoring -- V2Mon operates independent of VCC ˇ Watchdog timer with selectable timeout intervals ˇ Low VCC detection and reset assertion -- Four standard reset threshold voltages -- User programmable VTRIP threshold -- Reset signal valid to VCC=1V ˇ Low power CMOS -- 20ľA max standby current, watchdog on -- 1ľA standby current, watchdog OFF ˇ 64Kbits of EEPROM -- 64 byte page size ˇ Built-in inadvertent write protection -- Power-up/power-down protection circuitry -- Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512 bytes of EEPROM array with programmable Block LockTM protection ˇ 400kHz 2-wire interface --Slave addressing supports up to 4 devices on the same bus ˇ 2.7V to 5.5V power supply operation ˇ Available Packages -- 14-lead SOIC -- 14-lead TSSOP BLOCK DIAGRAM
V2MON V2 Monitor Logic Watchdog Transition Detector WP Data Register Command Decode & Control Logic VCC Threshold Reset logic Block Lock Control
The X40626 combines four popular functions, Power-on Reset Control, Watchdog Timer, Dual Supply Voltage Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time-out interval, the device activates the RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the set minimum VCC trip point. RESET is asserted until VCC returns to proper
+ VTRIP2 -
V2FAIL
Watchdog Timer Reset Protect Logic RESET Status Register Reset & Watchdog Timebase
SDA
SCL S0 S1
64KB EEPROM Array
VCC VTRIP
+ -
Power on and Low Voltage Reset Generation
REV 1.1.14 4/19/02
www.xicor.com
Characteristics subject to change without notice.
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X40626 Preliminary Information
operating level and stabilizes. Four industry standard Vtrip thresholds are available. However, Xicor's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Xicor's Block LockTM Protection. The array is internally organized as 64 bytes per page. The device features an 2-wire interface and software protocol allowing operation on an I2C bus. The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 page write cycles and a minimum data retention of 100 years. PIN CONFIGURATION
14 Pin SOIC/TSSOP NC S0 S1 NC RESET NC VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC NC WP V2MON V2FAIL SCL SDA
PIN FUNCTION Pin
1, 4, 6, 13 2 3 5
Name
NC S0 S1 RESET No Internal Connections Device Select Input Device Select Input
Function
Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for typically 200ms. RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog timeout period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET goes active on power up and remains active for typically 200ms after the power supply stabilizes. Ground Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time-out period results in RESET going active. Serial Clock. The Serial Clock controls the serial bus timing for data input and output. V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin. This circuit works independently from the Low VCC reset and battery switch circuits. Connect V2FAIL to VSS when not used. V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. There is no hysteresis in the V2MON comparator circuits. Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control register. Supply Voltage
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7 8
VSS SDA
9 10
SCL V2FAIL
11
V2MON
12 14
WP VCC
REV 1.1.14 4/19/02
www.xicor.com
Characteristics subject to change without notice.
X40626 Preliminary Information
PRINCIPLES OF OPERATION Power On Reset Application of power to the X40626 activates a Power On Reset Circuit that pulls the RESET pin active. This signal provides several benefits. It prevents the system microprocessor from starting to operate with insufficient voltage. It prevents the processor from operating prior to stabilization of the oscillator. It allows time for an FPGA to download its configuration prior to initialization of the circuit. It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power up. When VCC exceeds the device VTRIP threshold value for tPURST (200ms nominal) the circuit releases RESET allowing the system to begin operation. LOW VOLTAGE MONITORING During operation, the X40626 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. WATCHDOG TIMER The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL is HIGH (this is a start bit) prior to the expiration of the watchdog time-out period to prevent a RESET signal. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be "locked" by tying the WP pin HIGH. EEPROM INADVERTENT WRITE PROTECTION When RESET goes active as a result of a low voltage condition or Watchdog Timer Time-Out, any in-progress communications are terminated. While RESET is active, no new communications are allowed and no non-volatile write operation can start. Non-volatile writes in-progress when RESET goes active are allowed to finish. Additional protection mechanisms are provided with memory Block Lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. VCC/V2MON THRESHOLD RESET PROCEDURE The X40626 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X40626 threshold may be adjusted. The procedure is described below, and uses the application of a nonvolatile control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher or lower voltage value. It is necessary to reset the trip point before setting the new value. The VCC and V2MON must be tied together during this sequence.
Figure 1. Set VTRIP Level Sequence (VCC/V2MON = desired VTRIP values, WP = 12-15V when WEL bit set)
WP
VP = 12-15V
01234567 SCL
01234567
01234567
01234567
SDA A0H 00H xxH* *for VVTRIP2 address is 0DH for VTRIP address is 01H REV 1.1.14 4/19/02 00H
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Characteristics subject to change without notice.
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