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Details, datasheet, quote on part number:X5043
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| Part: | X5043 |
| Category: | Power Management => Supervisory Circuits => Microprocessor Supervisors |
| Description: | Cpu Supervisor With Selectable Watchdog Timer, Adjustable Low Voltage Reset, Active Low Reset |
| Company: | Xicor, Inc. |
| Datasheet: | Download X5043 datasheet File size : 109 kB |
| Request For quote: | Find where to buy X5043
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Datasheet text preview:
4K
X5043/X5045
CPU Supervisor with 4K SPI EEPROM
512 x 8 Bit
FEATURES · Selectable time out watchdog timer · Low VCC detection and reset assertion -- Five standard reset threshold voltages -- Re-program low VCC reset threshold voltage using special programming sequence. -- Reset signal valid to VCC = 1V · Long battery life with low power consumption -- <50µA max standby current, watchdog on -- <10µA max standby current, watchdog off -- <2mA max active current during read · 2.7V to 5.5V and 4.5V to 5.5V power supply versions · 4Kbits of EEPROM1M write cycle endurance · Save critical data with Block LockTM memory -- Protect 1/4, 1/2, all or none of EEPROM array · Built-in inadvertent write protection -- Write enable latch -- Write protect pin · 3.3MHz clock rate · Minimize programming time -- 16-byte page write mode -- Self-timed write cycle -- 5ms write cycle time (typical) · SPI modes (0,0 & 1,1) · Available packages -- 8-lead MSOP, 8-lead SOIC, 8-pin PDIP -- 14-lead TSSOP BLOCK DIAGRAM
Watchdog Transition Detector WP SI SO SCK Data Register Command Decode & Control Logic VCC Threshold Reset Logic
DESCRIPTION These devices combine four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/ RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.
Watchdog Timer Reset
Protect Logic RESET/RESET Status Register EEPROM Array 1Kbits 1Kbits 2Kbits Reset & Watchdog Timebase X5043 = RESET X5045 = RESET
CS/WDI
VCC VTRIP
+ -
Power on and Low Voltage Reset Generation
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice.
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X5043/X5045
The memory portion of the device is a CMOS Serial EEPROM array with Xicor's block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION
8-Lead SOIC/PDIP/MSOP CS/WDI SO WP VSS 1 2 3 4 X5043/45 8 7 6 5 VCC RESET/RESET SCK SI
Chip Select (CS) When CS is high, the X5043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043/45 will be in the standby power mode. CS low enables the X5043/45, placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low, nonvolatile writes to the X5043/45 are disabled, but the part otherwise functions normally. When WP is held high, all functions, including non volatile writes operate normally. WP going low while CS is still low will interrupt a write to the X5043/45. If the internal write cycle has already been initiated, WP going low will have no affect on a write. Reset (RESET, RESET) X5043/45, RESET/RESET is an active low/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of CS will reset the watchdog timer. PIN NAMES Symbol Description
Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Reset Output
14-Lead TSSOP CS SO NC NC NC WP VSS 1 2 3 4 5 6 7 X5043/45 14 13 12 11 10 9 8 VCC RESET/RESET NC NC NC SCK SI
PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input.
REV 1.1.2 5/29/01
CS SO SI SCK WP VSS VCC RESET/RESET
www.xicor.com
Characteristics subject to change without notice.
2 of 20
X5043/X5045
PRINCIPLES OF OPERATION Power On Reset Application of power to the X5043/X5045 activates a Power On Reset Circuit. This circuit pulls the RESET/ RESET pin active. RESET/RESET prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5043/X5045 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits. With no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure. VCC Threshold Reset Procedure The X5043/X5045 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5043/X5045 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to address 01h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 01h.
Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP value.)
WP VPE = 15-18V
CS 01234567 SCK 8 Bits SI 06h WREN 02h Write 01h Address 00h Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice.
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