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Details, datasheet, quote on part number:X5325V14
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| Part: | X5325V14 |
| Category: | Power Management => Supervisory Circuits => Microprocessor Supervisors |
| Description: | Cpu Supervisor With Selectable Watchdog Timer, Adjustable Low Voltage Reset, Active High Reset |
| Company: | Xicor, Inc. |
| Datasheet: | Download X5325V14 datasheet File size : 206 kB |
| Request For quote: | Find where to buy X5325V14
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Datasheet text preview:
Replaces X25323/X25325
X5323/X5325
CPU Supervisor with 32Kb SPI EEPROM
FEATURES ˇ Selectable watchdog timer ˇ Low VCC detection and reset assertion -- Five standard reset threshold voltages -- Re-program low VCC reset threshold voltage using special programming sequence -- Reset signal valid to VCC = 1V ˇ Determine watchdog or low voltage reset with a volatile flag bit ˇ Long battery life with low power consumption -- <50ľA max standby current, watchdog on -- <1ľA max standby current, watchdog off -- <400ľA max active current during read ˇ 32Kbits of EEPROM ˇ Built-in inadvertent write protection -- Power-up/power-down protection circuitry -- Protect 0, 1/4, 1/2 or all of EEPROM array with Block LockTM protection -- In circuit programmable ROM mode ˇ 2MHz SPI interface modes (0,0 & 1,1) ˇ Minimize EEPROM programming time -- 32-byte page write mode -- Self-timed write cycle -- 5ms write cycle time (typical) ˇ 2.7V to 5.5V and 4.5V to 5.5V power supply operation ˇ Available packages -- 14-lead TSSOP, 8-lead SOIC BLOCK DIAGRAM
Watchdog Transition Detector WP SI SO SCK CS/WDI Data Register Command Decode & Control Logic VCC Threshold Reset Logic Protect Logic RESET/RESET Status Register 8Kbits 8Kbits 16Kbits EEPROM Array Reset & Watchdog Timebase X5323 = RESET X5325 = RESET Watchdog Timer Reset
DESCRIPTION These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/ RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.
VCC VTRIP
+ -
Power On and Low Voltage Reset Generation
REV 1.1.2 11/13/01
www.xicor.com
Characteristics subject to change without notice.
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X5323/X5325
PIN CONFIGURATION
14-Lead TSSOP 8-Lead SOIC/PDIP CS/WDT SO WP VSS 1 2 3 4 X5323/25 8 7 6 5 VCC RESET/RESET SCK SI CS/WDT SO NC NC NC WP VSS 1 2 3 4 5 6 7 X5323/25 14 13 12 11 10 9 8 VCC RESET/RESET NC NC NC SCK SI
PIN DESCRIPTION Pin (SOIC/PDIP)
1
Pin TSSOP
1
Name
CS/WDI
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting of the watchdog timer control and the memory write protect bits. Ground Supply Voltage Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power up at about 1V and remains active for 200ms after the power supply stabilizes. No internal connections
2 5
2 8
SO SI
6
9
SCK
3 4 8 7
6 7 14 13
WP VSS VCC RESET/ RESET
3-5,10-12
NC
REV 1.1.2 11/13/01
www.xicor.com
Characteristics subject to change without notice.
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X5323/X5325
PRINCIPLES OF OPERATION Power On Reset Application of power to the X5323/X5325 activates a power on reset circuit. This circuit goes active at about 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. As long as RESET/RESET pin is active, the device will not respond to any Read/Write instruction. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5323/X5325 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The watchdog timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent a RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be "locked" by tying the WP pin LOW and setting the WPEN bit HIGH. VCC Threshold Reset Procedure The X5323/X5325 has a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or for higher precision in the VTRIP value, the X5323/ X5325 threshold may be adjusted. Setting the VTRIP Voltage This procedure sets the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure directly makes the change. If the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold to the Vcc pin and tie the CS/WDI pin and the WP pin HIGH. RESET/RESET and SO pins are left unconnected. Then apply the programming voltage VP to both SCK and SI and pulse CS/WDI LOW then HIGH. Remove VP and the sequence is complete. Figure 1. Set VTRIP Voltage
CS VP SCK VP SI
Resetting the VTRIP Voltage This procedure sets the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply a voltage between 2.7 and 5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin, and the SCK pin HIGH. RESET/RESET and SO pins are left unconnected. Then apply the programming voltage VP to the SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove VP and the sequence is complete. Figure 2. Reset VTRIP Voltage
CS VCC
SCK
VP SI
REV 1.1.2 11/13/01
www.xicor.com
Characteristics subject to change without notice.
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