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Details, datasheet, quote on part number:X76F041HE-3
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Datasheet text preview:
APPLICATION NOTE A V A I LABLE
AN83 · Development Tools XK76C
Password Access Security Supervisor 4K
X76F041
PASSTM SecureFlash
DESCRIPTION
4 x 128 x 8 Bit
FEATURES · 64-Bit Password Security · Three Password Modes -- Secure Read Access -- Secure Write Access -- Secure Configuration Access · Programmable Configuration -- Read, Write and Configuration Access Passwords -- Multiple Array Access/Functionality -- Retry Register/Counter · 8 Byte Sector Write · (4) 1K Memory Arrays · ISO Response to Reset · Low Power CMOS -- 50µ A Standby Current -- 3mA Active Current · 1.8V to 3.6V or 5V "Univolt" Read and Program Power Supply Versions · High Reliability -- Endurance: 100,000 Cycles -- Data Retention: 100 Years -- ESD Protection: 2000V on All Pins
The X76F041 is a password access security supervisor device, containing four 128 x 8 bit SecureFlash arrays. Access can be controlled by three 64-bit programmable passwords, one for read operations, one for write operations and one for device configuration. The X76F041 features a serial interface and software protocol allowing operation on a simple two wire bus. The bus signals are a clock input (SCL) and a bidirectional data input and output (SDA). Access to the device is controlled through a chip select input (CS), allowing any number of devices to share the same bus. The X76F041 also features a synchronous response to reset; providing an automatic output of a pre-configured 32-bit data stream conforming to the ISO standard for memory cards. The X76F041 utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
CHIP ENABLE DATA TRANSFER RETRY COUNTER SCL SDA INTERFACE LOGIC ARRAY ACCESS ENABLE 0800FF
CS
00007F
PASSWORD ARRAY AND PASSWORD VERIFICATION LOGIC
10017F
RST
ISO RESET RESPONSE DATA REGISTER
1801FF
CONFIGURATION REGISTER
(4) 16 x 64 SECUREFLASH ARRAYS
7002 ILL F01
©Xicor, Inc. 1994, 1995, 1996 Patents Pending 7002-2.2 4/30/97 T3/C0/D0 SH
1
Characteristics subject to change without notice
X76F041
PIN DESCRIPTION Serial Data Input/Output (SDA) SDA is a true three state serial data input/output pin. During a read cycle, data is shifted out on this pin. During a write cycle, data is shifted in on this pin. In all other cases this pin is in a high impedance state. Serial Clock (SCL) The Serial Clock controls the serial bus timing for data input and output. Chip Select (CS) When CS is HIGH, the X76F041 is deselected and the SDA pin is at high impedance and unless an internal write operation is underway the X76F041 will be in the standby power mode. CS LOW enables the X76F041, placing it in the active power mode. Reset (RST) RST is a device reset pin. When RST is pulsed HIGH while CS is LOW the X76F041 will output 32 bits of fixed data which conforms to the ISO standard for "synchronous response to reset". CS must remain LOW and the part must not be in a write cycle for the response to reset to occur. If at any time during the response to reset CS goes HIGH, the response to reset will be aborted and the part will return to the standby mode. PIN CONFIGURATION
DIP/SOIC
VCC RST SCL NC 1 2 3 4 8 VSS CS SDA NC
X76F041
7 6 5
7002 ILL F02
Symbol
CS SDA RST SCL VSS VCC NC
Description
Chip Select Input Serial Data Input/Output Reset Input Serial Clock Input Ground Supply Voltage No Connect
7002 FRM T01
2
F
X76F041
DEVICE OPERATION There are three primary modes of operation for the X76F041; READ, WRITE and CONFIGURATION. The READ and WRITE modes may be performed with or without an 8-byte password. The CONFIGURATION mode always requires an 8-byte password. The basic method of communication is established by first enabling the device (CS LOW), generating a start condition and then transmitting a command and address field followed by the correct password (if configured to require a password). All parts will be shipped from the factory in the non-password mode. The user must perform an ACK Polling routine to determine the validity of the password and start the data transfer (see Acknowledge Polling). Only after the correct password is accepted and an ACK Polling has been performed can the data transfer occur. To ensure correct communication, RST must remain LOW under all conditions except when initiating a "Response to Reset sequence". igure 1. X76F041 Device Operation
LOAD COMMAND+HIGH ORDER ADDRESS BYTE
Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device. If the X76F041 is in a nonvolatile write cycle a "no ACK" (SDA HIGH) response will be issued in response to loading of the command + high order address byte. If a stop condition is issued prior to the nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. The basic sequence is illustrated in Figure 1. After each transaction is completed, the X76F041 will reset and enter into a standby mode. This will also be the response if an attempt is made to access any limited array. Password Registers The three passwords, Read, Write and Configuration are stored in three 64 bit Write Only registers as illustrated in figure 2. Figure 2. Password Registers
63 64 BIT WRITE PASSWORD 64 BIT READ PASSWORD 0
LOAD LOW ORDER ADDRESS / CONFIGURATION INSTRUCTION BYTE
64 BIT CONFIGURATION PASSWORD
7002 ILL F04
LOAD 8BYTE PASSWORD (IF APPLICABLE)
VERIFY PASSWORD ACCEPTANCE BY USE OF ACK POLLING (IF APPLICABLE)
Device Configuration Five 8-Bit configuration registers are used to configure the X76F041. These are shown in figure 3. Figure 3. Configuration Registers
READ / WRITE DATA BYTES
7002 ILL F03
63 ACR1 ACR2 CR RR RC RES RES RES
0
RESERVED RETRY COUNTER RETRY REGISTER CONFIGURATION REGISTER ARRAY CONTROL REGISTER 2 ARRAY CONTROL REGISTER 1 7002 ILL F04B
3
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