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Details, datasheet, quote on part number:X88257S
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Datasheet text preview:
X88257 8051 Microcontroller Family Compatible 256K
X88257
E2 Micro-Peripheral
DESCRIPTION
32,768 x 8 Bit
FEATURES · Multiplexed Address/Data Bus --Direct Interface to Popular 8051 Family · High Performance CMOS --Fast Access Time, 120ns --Low Power --60mA Active Maximum --500µA Standby Maximum · Software Data Protection · Toggle Bit Polling --Early End of Write Detection · Page Mode Write --Allows up to 128 Bytes to be Written in One Write Cycle · High Reliability --Endurance: 10,000 Write Cycle --Data Retention: 100 Years · 28-Lead PDIP Package · 28-Lead SOIC Package · 32-Lead PLCC Package
The X88257 is an 32K x 8 E2PROM fabricated with advanced CMOS Textured Poly Floating Gate Technology. The X88257 features a multiplexed address and data bus allowing direct interface to a variety of popular single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface circuitry.
FUNCTIONAL DIAGRAM
CE, CE WR RD PSEN A8A14 CONTROL LOGIC X D E C O D E SOFTWARE DATA PROTECT
ALE
L A T C H E S
32K x 8 E2PROM
Y DECODE I/O & ADDRESS LATCHES AND BUFFERS A/D0A/D7
6509 ILL F02.1
© Xicor, Inc. 1994-1997 Patents Pending 6509-1.9 4/9/96 T2/C5/D8 NS
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Characteristics subject to change without notice
X88257
PIN DESCRIPTIONS Address/Data (A/D0A/D7) Multiplexed low-order addresses and data. The addresses flow into the device while ALE is HIGH. After ALE transitions from a HIGH to LOW the addresses are latched. Once the addresses are latched these pins input data or output data depending on RD, WR, PSEN, and CE. Addresses (A8A14) High order addresses flow into the device when ALE = VIH and are latched when ALE goes LOW. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, ALE is LOW, and CE is LOW, the X88257 is placed in the low power standby mode. If CE is used to select the device, the CE must be tied LOW. Chip Enable (CE) Chip enable is active HIGH. When CE is used to select the device, the CE must be tied HIGH. Program Store Enable (PSEN) When the X88257 is to be used in a 8051-based system, PSEN is tied directly to the microcontroller's PSEN output. Read (RD) When the X88257 is to be used in a 8051-based system, RD is tied directly to the microcontroller's RD output. Write (WR) When the X88257 is to be used in a 8051-based system, WR is tied directly to the microcontroller's WR output. Address Latch Enable (ALE) Addresses flow through the latches to address decoders when ALE is HIGH and are latched when ALE transitions from a HIGH to LOW. PIN NAMES Symbol ALE A/D0A/D7 A8A14 RD WR PSEN CE, CE VSS VCC NC
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PSEN CE NC NC NC NC NC NC A/D0 5 6 7 8 9 10 11 12 X88257
A14 A12 ALE PSEN CE NC NC NC NC NC A/D0 A/D1 A/D2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PIN CONFIGURATION
PDIP SOIC 28 27 26 25 24 23 X88257 22 21 20 19 18 17 16 15 VCC WR A13 A8 A9 A11 RD A10 CE A/D7 A/D6 A/D5 A/D4 A/D3
6509 FHD F01.3
PLCC
ALE VCC A12 A14 NC WR A13
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3
2
1 32 31 30 29 28 27 26 25 24 23 22
A8 A9 A11 NC RD A10 CE A/D7 A/D6
13 21 14 15 16 17 18 19 20
A/D1 A/D2 VSS A/D3 A/D4 A/D5 NC
6509 FHD F01A.5
Description Address Latch Enable Address Inputs/Data I/O Address Inputs Read Input Write Input Program Store Enable Input Chip Enable Ground Supply Voltage No Connect
6509 PGM T01.1
X88257
TYPICAL APPLICATION
U? 31 19 EA/VP X1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE/P TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 11 12 12 15 16 17 18 19 A/D0 A/D1 A/D2 A/D3 A/D4 A/D5 A/D6 A/D7
18 9
X2 RESET
12 13 14 15 1 2 3 4 5 6 7 8
INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 8051
25 A8 24 A9 21 A10 23 A11 2 A12 26 A13 1 A14 20 CE CE 22 RD 27 WR 4 PSEN 3 ALE X88257
6509 ILL F03.3
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PRINCIPLES OF OPERATION The X88257 is a highly integrated peripheral device for a wide variety of single-chip microcontrollers. The X88257 provides 32K-bytes of 5V E2PROM which can be used either for program storage, data storage or a combination of both, in systems based upon Harvard (80XX) architectures. The X88257 incorporates the interface circuitry normally needed to decode the control signals and demultiplex the address/data bus to provide a "seamless" interface. The interface inputs on the X88257 are configured such that it is possible to directly connect them to the proper interface signals of the appropriate single-chip microcontroller. In the Harvard type system, the reading of data from the chip is controlled either by the PSEN or the RD signal, which essentially maps the X88257 into both the Program and the Data Memory address map. The X88257 also features the industry standard 5V E2PROM characteristics such as byte or page mode write and Toggle Bit Polling.
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DEVICE OPERATION Modes--Mixed Program/Data Memory By properly assigning the address spaces, a single X88257 can be used as both the program and data memory. This would be accomplished by connecting all the 8051 control outputs to the corresponding inputs of the X88257. Program Memory Mode This mode of operation is read-only. The PSEN and ALE inputs of the X88257 are tied directly to the PSEN and ALE outputs of the microcontroller. The RD and WR inputs are tied HIGH. When ALE is HIGH, the A/D0A/D7 and A8A14 addresses flow into the device. The addresses, both lowand high-order, are latched when ALE transitions LOW (VIL). PSEN will then go LOW and after tPLDV; Valid data is presented on the A/D0A/D7 pins. CE must be LOW during the entire operation.
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