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Details, datasheet, quote on part number:X9407
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Datasheet text preview:
APPLICATION NOTES AVAILABLE
AN99 · AN115 · AN124 · AN133 · AN134 · AN135
Low Noise/Low Power/2-Wire Bus
X9407
Quad Digitally Controlled (XDCPTM) Potentiometers
FEATURES · · · · · · · · Four potentiometers in one package 64 resistor taps per potentiometer 2-wire serial interface Wiper resistance, 40 typical at 5V Four nonvolatile data registers for each pot Nonvolatile storage of wiper position Standby current < 1µA max (total package) VCC = 2.7V to 5.5V operation V+ = 2.7V to 5.5V V = 2.7V to 5.5V · 10K, 2.5K end to end resistances · High reliability -- Endurance100,000 data changes per bit per register -- Register data retention100 years · 24-lead SOIC, 24-lead TSSOP, and 24-lead XBGA packages DESCRIPTION The X9407 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC VSS V+ VR0 R1 Pot 0 Wiper Counter Register (WCR) RH0 R0 R1 Wiper Counter Register (WCR) RH2
WP SCL SDA A0 A1 A2 A3 Interface and Control Circuitry Data
R2 R3
RL0 RW0
R2 R3
Resistor Array Pot 2
RL2 RW2
8 RW1 R0 R1 Wiper Counter Register (WCR) Resistor Array Pot 1 RH1 R0 R1 Wiper Counter Register (WCR) RW3 RH3
R2 R3
RL1
R2 R3
Resistor Array Pot 3
RL3
REV 1.4 7/22/02
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Characteristics subject to change without notice.
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X9407
PIN DESCRIPTIONS Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9407. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Device Address (A0A3) The address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9407. A maximum of 16 devices may occupy the 2-wire serial bus. Potentiometer Pins RH (RH0RH3), RL (RL0RL3) The RH and RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer.
RW (RW0RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when low prevents nonvolatile writes to the Data Registers. Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages for the XDCP analog section. PIN NAMES Symbol
SCL SDA A0-A3 RH0RH3, RL0RL3 RW0RW3 WP V+,VVCC VSS NC
Description
Serial Clock Serial Data Device Address Potentiometer Pins (terminal equivalent) Potentiometer Pins (wiper equivalent) Hardware Write Protection Analog Supplies System Supply Voltage System Ground No Connection
PIN CONFIGURATION
DIP/SOIC VCC RL0 RH0 RW0 A2 WP SDA A1 RL1 RH1 RW1 V
SS
XBGA 24 23 22 21 20 19 18 17 16 15 14 13 V+ RL3 RH3 RW3 A0 NC A3 SCL RL2 RH2 RW2 VF A B C D E 1
RW0 RL0 VCC V+
TSSOP 3
A1
1 2 3 4 5 6 7 8 9 10 11 12 X9407
2
A2 WP RH0
4
RL1 RW1 VSS V-
SDA A1 RL1 RH1 RW1 VSS VRW2 RH2 RL2 SCL
1 2 3 4 5 6 7 8 9 10 11 12 X9407
24 23 22 21 20 19 18 17 16 15 14 13
WP A2 RW0 RH0 RL0 VCC V+ RL3 RH3 RW3 A0 NC
SDA RH1
RH3
NC A0
RH2
A3 SCL
RL3 RW3
RW2 RL2
Top ViewBumps Down
A3
REV 1.4 7/22/02
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Characteristics subject to change without notice.
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X9407
PRINCIPLES OF OPERATION The X9407 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9407 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9407 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9407 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9407 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9407 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9407 will respond with a final acknowledge. Array Description The X9407 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RLinputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9407 this is fixed as 0101[B]. Figure 1. Slave Address
Device Type Identifier
0
1
0
1
A3
A2
A1
A0
Device Address
The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0-A3 inputs. The X9407 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9407 to respond with an acknowledge. The A0A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS.
Characteristics subject to change without notice.
REV 1.4 7/22/02
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