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Details, datasheet, quote on part number:X9428YVI
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| Part: | X9428YVI |
| Category: | Analog & Mixed-Signal Processing => Potentiometers => Digital Potentiometers |
| Description: | Single 64 Tap Xdcp, Low Power Two-wire Interface, Dual Supply |
| Company: | Xicor, Inc. |
| Datasheet: | Download X9428YVI datasheet File size : 593 kB |
| Request For quote: | Find where to buy X9428YVI
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Datasheet text preview:
APPLICATION NOTES AVAILABLE
AN99 ˇ AN115 ˇ AN120 ˇ AN124 ˇ AN133 ˇ AN134 ˇ AN135
Low Noise/Low Power/2-Wire Bus
X9428
Single Digitally Controlled Potentiometer (XDCPTM)
FEATURES ˇ Solid state potentiometer ˇ 2-wire serial interface ˇ Register oriented format -- Direct Read/Write/Transfer Wiper Position -- Store as many as Four Positions per Potentiometer ˇ Power supplies -- VCC = 2.7V to 5.5V -- V+ = 2.7V to 5.5V -- V = 2.7V to 5.5V ˇ Low power CMOS -- Standby current < 1ľA -- Ideal for Battery Operated Applications ˇ High reliability -- Endurance100,000 Data Changes per Bit per Register -- Register Data Retention100 years ˇ 4-bytes of nonvolatile memory ˇ 10K Ohm resistor array ˇ Resolution: 64 taps each potentiometer ˇ SOIC and TSSOP packages DESCRIPTION The X9428 integrates a digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC VSS V+ V R0 R1 Interface and Control Circuitry Data WP VH/RH
SCL SDA A0 A2 A3
8
R2 R3
Wiper Counter Register (WCR)
VL/RL VW/RW
REV 1.1.5 7/8/03
www.xicor.com
Characteristics subject to change without notice.
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X9428
PIN DESCRIPTIONS Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9428. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Device Address (A0, A2, A3) The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9428. A maximum of 8 devices may occupy the 2-wire serial bus. Potentiometer Pins RH/VH, RL/VL The RH/VH and RL/VL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. RW/VW The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input WP The WP pin when low prevents nonvolatile writes to the Data Registers. Analog Supply V+, VThe Analog Supply V+, V- are the supply voltages for the XDCP analog section. PIN NAMES Symbol
SCL SDA A0, A2, A3 RH/VH, VL/RH RW/VW WP V+,VVCC VSS NC Serial clock Serial data Device address Potentiometer Pins (terminal equivalent) Potentiometer Pin (wiper equivalent) Hardware write protection Analog and voltage follower System supply voltage System ground No connection
VCC A2 RL/VL RH/VH RW/VW SDA WP VSS 1 2 3 4 5 6 7 8 X9428
PIN CONFIGURATION
DIP/SOIC 16 15 14 13 12 11 10 9 V+ NC A0 NC A3 SCL NC V
TSSOP A2 RL RH RW SDA WP VSS 1 2 3 4 5 6 7 X9428 14 13 12 11 10 9 8 VCC V+ A0 NC A3 SCL V
Description
REV 1.1.5 7/8/03
www.xicor.com
Characteristics subject to change without notice.
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X9428
PRINCIPLES OF OPERATION The X9428 is a highly integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9428 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9428 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9428 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9428 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9428 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9428 will respond with a final acknowledge. Array Description The X9428 is comprised of a resistor array. The array contains 63 discrete resistive segments that are connected in series. The physical ends of the array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of the array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9428 this is fixed as 0101[B]. Figure 1. Slave Address
Device Type Identifier
0
1
0
1
A3
A2
0
A0
Device Address
The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0, A2, A3 inputs. The X9428 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9428 to respond with an acknowledge. The A0, A2, A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS.
Characteristics subject to change without notice.
REV 1.1.5 7/8/03
www.xicor.com
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