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Details, datasheet, quote on part number:XM28C020-12
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Datasheet text preview:
XM28C020 2 Megabit Module
XM28C020
5 Volt, Byte Alterable E2PROM
DESCRIPTION
256K x 8 Bit
TYPICAL FEATURES
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High Density 2 Megabit (256K x 8) Module Access Time of 150ns at 55°C to +125°C Base Memory Component: Xicor X28C513 Pinout conforms to JEDEC Standard for 2 Megabit E2PROM Fast Write Cycle Times --128 Byte Page Write --Byte or Page Write Cycle: 5ms Typical --Complete Memory Rewrite: 10 Seconds Early End of Write Detection --DATA Polling --Toggle Bit Polling Software Data Protection Three Temperature Ranges --Commercial: 0°C to +75°C --Industrial: 40° to +85°C --Military: 55° to +125°C High Rel Module --100% MIL-STD-883 Compliant Components Endurance: 100,000 Cycles
The XM28C020 is a high density 2 Megabit E2PROM comprised of four X28C513 LCCs mounted on a co-fired multilayered ceramic substrate. Individual components are 100% tested prior to assembly in module form and then 100% tested after assembly. The XM28C020 is configured 256K x 8 bit. The module supports a 128-byte page write operation. This combined with DATA Polling or Toggle Bit Polling, effectively provides a 39µs/byte write cycle, enabling the entire array to be rewritten in 10 seconds. The XM28C020 provides the same high endurance and data retention as the X28C513.
FUNCTIONAL DIAGRAM
X28C513 A0A15 I/O0I/O7 OE WE CE X28C513 A0A15 I/O0I/O7 OE WE CE
PIN CONFIGURATION
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 XM28C020
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/04 I/O3
A0A15 I/O0I/O7 OE WE CE A16 A17
X28C513 A0A15 I/O0I/O7 OE WE CE
X28C513 A0A15 I/O0I/O7 OE WE CE
3872 FHD F02
3872 FHD F01
© Xicor, Inc. 1991, 1995, 1996 Patents Pending 3872-1.9 6/18/97 T1/C0/D0 SH
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Characteristics subject to change without notice
XM28C020
PIN DESCRIPTIONS Addresses (A0A17) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced (see Note 4). Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0I/O7) Data is written to or read from the XM28C020 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the XM28C020. PIN NAMES Symbol A0A17 I/O0I/O7 WE CE OE VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
3872 PGM T01
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XM28C020
DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The XM28C020 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms (see Note 4). Page Write Operation The page write feature of the XM28C020 allows the entire memory to be written in 10 seconds. Page write allows two to 128 bytes of data to be consecutively written to the XM28C020 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A17) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to 127 bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page DATA Polling (I/O7) The XM28C020 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the XM28C020, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the XM28C020 is in the protected state and an illegal write operation is attempted, DATA Polling will not operate. Toggle Bit (I/O6) The XM28C020 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from "1" to "0" and "0" to "1" on subsequent attempts to read the last byte written. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs. Write Operation Status Bits The XM28C020 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
RESERVED TOGGLE BIT DATA POLLING
3872 FHD F09
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