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Part: 5962R01525
Category:
Description: Qpro XQ/XQR18V04 QML Programmable Configuration Proms
Company: Xilinx Corp.
Datasheet: Download 5962R01525 datasheet File size : 132 kB
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QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
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DS082 (v1.2) November 5, 2001
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Preliminary Product Specification
Features
· In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs · · · Endurance of 2,000 program/erase cycles Program/erase over full military temperature range
Radiation Hardenned XQR18V04
· · · · Fabricated on Epitaxial Substrate Latch-Up Immune to >120 LET Guaranteed TID of 40 kRad(Si) Suppor ts SEU Scrubbing
IEEE Std 1149.1 boundary-scan (JTAG) support Cascadable for storing longer or multiple bitstreams Dual configuration modes Serial Slow/Fast configuration (up to 33 MHz) Parallel (up to 264 Mbps at 33 MHz)
Description
Xilinx introduces the QProTM XQ18V04 and XQR18V04 ser ies of QML in-system programmable and radiation hardened configuration PROMs. Initial devices in this 3.3V family are a 4-megabit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA configuration bitstreams. W hen the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Ser ial mode, the PROM and the FPGA are clocked by an exter nal clock. W hen the FPGA is in Express or SelectMAP Mode, an exter nal oscillator will generate the configuration clock that dr ives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. Neither Express nor SelectMAP utilize a Length Count, so a free-running oscillator may be used. See Figure 6.
OE/Reset
· · · · · · ·
Low -power advanced CMOS FLASH process 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals. 3.3V or 2.5V output capability Available in CC44 and VQ44 packages. Design support using the Xilinx AllianceTM and FoundationTM series software packages. JTAG command initiation of standard FPGA configuration. Available to Standard Microcircuit Drawing 5962-01525. For more information contact Defense Supply Center Columbus (DSCC) at http://www.dscc.dla.mil
CLK CE
TCK TMS TDI TDO
Control and JTAG Interface
Data Memor y Address Data Serial or Parallel Interface
7
CEO D0 DATA (Serial or Parallel [Express/SelectMAP] Mode) D[1:7] Express Mode and SelectMAP Interface
CF
DS026_01_021000
Figure 1: XQ18V04 Series Block Diagram
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
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QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this
R
chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC1700L one-time programmable Serial PROM family.
Pinout and Pin Description
Table 1: Pin Names and Descriptions (pins not listed are "no connect") Pin Name D0 Boundary Scan Order 4 3 D1 6 5 D2 2 1 D3 8 7 D4 24 23 D5 10 9 D6 17 16 D7 14 13 CLK OE / RESET 0 20 19 18 CE 15 44-pin Function DATA OUT OU T P U T ENABLE DATA OUT OU T P U T ENABLE DATA OUT OU T P U T ENABLE DATA OUT OU T P U T ENABLE DATA OUT OUT P UT ENABLE DATA OUT OU T P U T ENABLE DATA OUT OUT P UT ENABLE DATA OUT OUT P UT ENABLE DATA IN DATA IN DATA OUT OUT P UT ENABLE DATA IN Each rising edge on the CLK input increments the internal address counter if both CE is Low and OE/RESET is High. When Low, this input holds the address counter reset and the DATA output is in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is NOT programmable. When CE is High, this pin puts the device into standby mode and resets the address counter. The DATA output pin is in a high-impedance state, and the device is in low power standby mode. 43 13 5 19 19 25 14 20 25 31 9 15 27 33 Pin Description D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. VQFP 40 44-pin CLCC 2
D0-D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in Express/SelectMap mode.
29
35
42
4
15
21
2
www.xilinx.com 1-800-255-7778
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
Table 1: Pin Names and Descriptions (pins not listed are "no connect") (Continued) Pin Name CF Boundary Scan Order 22 21 44-pin Function DATA OUT OUT P UT ENABLE DATA OUT OUT P UT ENABLE Pin Description Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command. Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. When OE/RESET goes Low, CEO stays High until the PROM is brought out of reset by bringing OE/RESET High. GND is the ground connection. VQFP 10 44-pin CLCC 16
CE O
13 14
21
27
G ND
6, 18, 28 & 41 5
3, 12, 24 & 34 11
TMS
MODE SELECT
The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the device if the pin is not driven. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. Positive 3.3V supply voltage for internal logic and input buffers. Positive 3.3V or 2.5V supply voltage connected to the output voltage drivers.
TCK
C LOCK
7
13
TDI
DATA IN
3
9
TDO
DATA OUT
31
37
V CC V CCO
17, 35 & 38 8, 16, 26 & 36
23, 41 & 44 14, 22, 32 & 42
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
3
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
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Xilinx FPGAs and Compatible PROMs
Device X QV 1 0 0 X QV ( R ) 3 0 0 X QV ( R ) 6 0 0 XQV(R)1000 X QV ( R ) 6 0 0 E XQV(R)1000E XQV(R)2000E Configuration Bits 781, 216 1, 751, 808 3, 607, 968 6, 127, 744 3, 961, 632 6, 587, 520 10,159,648 XQ(R)18VO4 PROMs 1 1 1 2 1 2 3
In-System Programming
In-System Programmable PROMs can be programmed individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 2. In-system programming offers quick and efficient design iterations and eliminates unnecessar y package handling or socketing of devices. The Xilinx development system provides the programming data sequence using either Xilinx JTAG Programmer software and a download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The JTAG Programmer software also outputs ser ial vector format (SVF) files for use with any tools that accept SVF format and with automatic test equipment. All outputs are held in a high-impedance state or held at clamp levels during in-system programming.
Capacity
Devi ces XQ(R)18V04 Configuration Bits 4,194,304
OE/RESET
The ISP programming algorithm requires issuance of a reset that will cause OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by the Xilinx HW-130 device programmer. This provides the added flexibility of using pre-programmed devices in board design and boundary-scan manufacturing tools, with an in-system programmable option for future enhancements and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaranteed endurance level of 2,000 in-system program/erase cycles and a minimum data retention of ten years. Each device meets all functional, performance, and data retention specifications within this endurance limit.
Design Security
The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the programming data against unauthorized reading. Table 2 shows the security setting available. The read security bit can be set by the user to prevent the inter nal programming pattern from being read or copied via JTAG. When set, it allows device erase. Erasing the entire device is the only way to reset the read security bit. Table 2: Data Security Options Default = Reset Read Allowed Program/Erase Allowed S et Read Inhibited via JTAG Erase Allowed
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www.xilinx.com 1-800-255-7778
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
V CC
GND
(a)
(b)
DS026_02_011100
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
IEEE 1149.1 Boundary-Scan (JTAG)
The XQ(R)18V04 family is fully compliant with the IEEE Std. 1149.1 Boundary-Scan, also known as JTAG. A Test Access Port (TAP) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the XQ(R)18V04 device. Table 3 lists the required and optional boundary-scan instructions supported in the XQ(R)18V04. Refer to the IEEE Std. 1149.1 specification for a complete description of boundar y-scan architecture and the required and optional instructions.
Table 3: Boundary Scan Instructions Boundary-Scan Command Binary Code [7:0] Description
Required Instructions BYPASS SAMPLE/ PRELOAD EXTEST 11 111111 00 000001 Enables BYPASS Enables boundary-scan SAMPLE/PRELOAD operation Enables boundary-scan EXTEST operation
00 000000
Optional Instructions CLAMP HIGHZ 11 111010 11 111100 Enables boundary-scan CLAMP operation All outputs in high-impedance state simultaneously Enables shifting out 32-bit IDCODE Enables shifting out 32-bit USERCODE
I DCOD E US E RCOD E
11 111110 11 111101
XQ(R)18V04 Specific Instructions CONFIG 11 101110 Initiates FPGA configuration by pulsing CF pin Low
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
5
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