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Details, datasheet, quote on part number:XC17V08VQ44C
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Datasheet text preview:
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XC17V00 Series Configuration PROMs
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DS073 (v1.10) April 14, 2002
Preliminary Product Specification · · · · Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20 Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages. Dual configuration modes for the XC17V16 and XC17V08 devices · Ser ial slow/fast configuration (up to 33 Mb/s) Parallel (up to 264 Mb/s at 33 MHz)
Features
· One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions Low -power CMOS Floating Gate process 3.3V supply voltage
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Guaranteed 20 year life data retention
Description
Xilinx introduces the high-density XC17V00 family of configuration PROMs which provide an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. Initial devices in the 3.3V family are available in 16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1 and Figure 2 for simplified block diagrams of the XC17V00 family. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. W hen the FPGA is in SelectMAP mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator can be used to drive CCLK. See Figure 3. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS073 (v1.10) April 14, 2002 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
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XC17V00 Series Configuration PROMs
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VCC
VPP
GND
RESET/ OE or OE/ RESET
CE
CEO
CLK
Address Counter
TC
EPROM Cell Matrix
Output
OE DATA
DS073_01_072600
Figure 1: Simplified Block Diagram for XC17V04, XC17V02, and XC17V01 (does not show programming circuit)
VCC
VPP
GND
RESET/ OE or OE/ RESET
CE
CEO
CLK
Address Counter
TC
BUSY EPROM Cell Matrix Output 8 OE D0 Data (Serial or Parallel Mode)
7 7
D[1:7] (SelectMAP Interface)
DS073_02_072600
Figure 2: Simplified Block Diagram for XC17V16 and XC17V08 (does not show programming circuit)
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www.xilinx.com 1-800-255-7778
DS073 (v1.10) April 14, 2002 Preliminary Product Specification
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XC17V00 Series Configuration PROMs
Pin Description
DATA[0:7]
Data output is in a high-impedance state when either CE or OE are inactive. During programming, the D0 pin is I/O. Note that OE can be programmed to be either active High or active Low.
Note: XC17V04, XC17V02, and XC17V01 have serial output only.
VPP
Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating!
CLK
Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active.
VCC and GND
Positive supply and ground pins.
PROM Pinouts for XC17V16 and XC17V08
Pins not listed are "no connect." 44-pin VQFP (VQ44) 24 40 29 42 27 9 25 14 19 43 13 15 6, 18, 28, 37, 41 21 35 8, 16, 17, 26, 36, 38 44-pin PLCC (PC44) 30 2 35 4 33 15 31 20 25 5 19 21 3, 12, 24, 34, 43 27 41 14, 22, 23, 32, 42, 44
RESET/OE
When High, this input holds the address counter reset and puts the DATA output in a high-impedance state. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at "0", and puts the DATA output in a high-impedance state. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can connected to the FPGAs INIT pin and a pullup resistor. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 Programmer. Third-party programmers have different methods to invert this pin.
Pin Name BUSY D0 D1 D2 D3 D4 D5 D6 D7 CLK RESET/OE (OE/RESET) CE GND CE O VPP V CC
CE
When High, this pin disables the internal address counter, puts the DATA output in a high-impedance state, and forces the device into low-ICC standby mode.
CEO
Chip Enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low.
Capacity
Devices XC17V16 XC17V08 Configuration Bits 16,777,216 8, 388, 608
BUSY (XC17V16 and XC17V08 only)
If BUSY pin is floating, the user must program the BUSY bit which will cause BUSY pin to be internally tied to a pull-down resistor. When asserted High, output data are held and when BUSY pin goes Low, data output will resume.
DS073 (v1.10) April 14, 2002 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
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