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Details, datasheet, quote on part number:XC2S400E-6FT256I
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Spartan-IIE 1.8V FPGA Family: Complete Data Sheet
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DS077 July 9, 2003
Product Specification
This document includes all four modules of the SpartanTM-IIE FPGA data sheet.
Module 1: Introduction and Ordering Information
DS077-1 (v2.1) July 9, 2003 4 pages · · · · · · Introduction Features General Overview Product Availability User I/O Chart Ordering Information
Module 3: DC and Switching Characteristics
DS077-3 (v2.1) July 9, 2003 22 pages · DC Specifications - Absolute Maximum Ratings - Recommended Operating Conditions - DC Characteristics - Power-On Requirements - DC Input and Output Levels Switching Characteristics - Pin-to-Pin Parameters - IOB Switching Characteristics - Clock Distribution Characteristics - DLL Timing Parameters - CLB Switching Characteristics - Block RAM Switching Characteristics - TBUF Switching Characteristics - JTAG Switching Characteristics - Configuration Switching Characteristics
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Module 2: Functional Description
DS077-2 (v2.1) July 9, 2003 20 pages · Architectural Description - Spar tan-IIE Array - Input/Output Block - Configurable Logic Block - Block RAM - Clock Distribution: Delay-Locked Loop - Boundary Scan Development System Configuration
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Module 4: Pinout Tables
DS077-4 (2.1) February 14, 2003 54 pages · · Pin Definitions Pinout Tables
IMPORTANT NOTE: The Spartan-IIE 1.8V FPGA data sheet is created and published in separate modules. This complete version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS077 July 9, 2003 Product Specification
www.xilinx.com 1-800-255-7778
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Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
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DS077-1 (v2.1) July 9, 2003
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Product Specification · System level features - SelectRAM+TM hierarchical memory: · 16 bits/LUT distributed RAM · Configurable 4K-bit true dual-port block RAM · Fast interfaces to external RAM - Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant - Low-power segmented routing architecture - Dedicated carry logic for high-speed arithmetic - Efficient multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with enable, set, reset - Four dedicated DLLs for advanced clock control · Eliminate clock distribution delay · Multiply, divide, or phase shift - Four primary low-skew global clock distribution nets - IEEE 1149.1 compatible boundary scan logic Versatile I/O and packaging - Low cost packages available in all densities - Family footprint compatibility in common packages - 19 high-performance interface standards · LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL · LVDS and LVPECL differential I/O - Up to 205 differential I/O pairs that can be input, output, or bidirectional - Hot swap I/O (CompactPCI friendly) Fully supported by powerful Xilinx ISE development system - Fully automatic mapping, placement, and routing - Integrated with design entry and verification tools - Extensive IP library including DSP functions and soft processors Maximum Available User I/O(1) 182 202 265 289 329 410 514 Maximum Differential I/O Pairs 83 86 114 120 120 172 205
Introduction
The SpartanTM-IIE 1.8V Field-Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The seven-member family offers densities ranging from 50,000 to 600,000 system gates, as shown in Table 1. System performance is supported beyond 200 MHz. Spartan-IIE devices deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined architecture based on the proven VirtexTM-E platform. Features include block RAM (to 288K bits), distributed RAM (to 221,184 bits), 19 selectable I/O standards, and four DLLs (Delay-Locked Loops). Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The Spartan-IIE family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).
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Features
· Second generation ASIC replacement technology - Densities as high as 15,552 logic cells with up to 600,000 system gates - Streamlined features based on Virtex-E architecture - Unlimited in-system reprogrammability - Very low cost
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Table 1: Spartan-IIE FPGA Family Members Logic Cells 1,728 2,700 3,888 5,292 6,912 10,800 15,552 Typical System Gate Range (Logic and RAM) 23,000 - 50,000 37,000 - 100,000 52,000 - 150,000 71,000 - 200,000 93,000 - 300,000 145,000 - 400,000 210,000 - 600,000 CLB Array (R x C) 16 x 24 20 x 30 24 x 36 28 x 42 32 x 48 40 x 60 48 x 72 Total CLBs 384 600 864 1,176 1,536 2,400 3,456 Distributed RAM Bits 24,576 38,400 55,296 75,264 98,304 153,600 221,184 Block RAM Bits 32K 40K 48K 56K 64K 160K 288K
Device XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E
Notes: 1. User I/O counts include the four global clock/user input pins. See details in Table 3, page 3
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS077-1 (v2.1) July 9, 2003 Product Specification
www.xilinx.com 1-800-255-7778
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Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
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General Overview
The Spartan-IIE family of FPGAs have a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked Loops (DLLs), one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. The XC2S400E has four columns and the XC2S600E has six columns of block RAM. These functional elements are interconnected by a powerful hierarchy of versatile routing channels (see Figure 1). Spar tan-IIE FPGAs are customized by loading configuration data into internal static memory cells. Unlimited reprogramming cycles are possible with this approach. Stored values in these cells determine logic functions and interconnections implemented in the FPGA. Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes. Xilinx offers multiple types of low-cost configuration solutions including the Platform Flash in-system programmable configuration PROMs. Spar tan-IIE FPGAs are typically used in high-volume applications where the versatility of a fast programmable solution adds benefits. Spartan-IIE FPGAs are ideal for shortening product development cycles while offering a cost-effective solution for high volume production.
Spartan-IIE FPGAs achieve high-performance, low-cost operation through advanced architecture and semiconductor technology. Spartan-IIE devices provide system clock rates beyond 200 MHz. Spartan-IIE FPGAs offer the most cost-effective solution while maintaining leading edge performance. In addition to the conventional benefits of high-volume programmable logic solutions, Spartan-IIE FPGAs also offer on-chip synchronous single-port and dual-por t RAM (block and distributed form), DLL clock drivers, programmable set and reset on all flip-flops, fast carry logic, and many other features.
Spartan-IIE Family Compared to Spartan-II Family
· · · · · Higher density and more I/O Higher performance Unique pinouts in cost-effective packages Differential signaling - LVDS, Bus LVDS, LVPECL VCCINT = 1.8V - Lower power - 5V tolerance with external resistor - 3V tolerance directly PCI, LVTTL, and LVCMOS2 input buffers powered by VCCO instead of VCCINT Unique larger bitstream
DLL
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DLL
BLOCK RAM
CLBs
CLBs
BLOCK RAM
CLBs
CLBs
DLL
I/O LOGIC
DS077_01_052102
Figure 1: Basic Spartan-IIE Family FPGA Block Diagram
2 www.xilinx.com 1-800-255-7778 DS077-1 (v2.1) July 9, 2003 Product Specification
BLOCK RAM
DLL
BLOCK RAM
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