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Details, datasheet, quote on part number:XC2V40-4CS144I
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VirtexTM-II Platform FPGAs: Complete Data Sheet
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DS031 October 14, 2003
Product Specification
This document includes all four modules of the Virtex-II Platform FPGA data sheet.
Module 1: Introduction and Overview
DS031-1 (v2.0) August 1, 2003 7 pages · · · · Summary of Features General Description Device/Package Combinations and Maximum I/O Ordering Information
Module 3: DC and Switching Characteristics
DS031-3 (v3.1) October 14, 2003 38 pages · · · · · · Electrical Characteristics Performance Characteristics Switching Characteristics Pin-to-Pin Output Parameter Guidelines Pin-to-Pin Input Parameter Guidelines DCM Timing Parameters
Module 2: Functional Description
DS031-2 (v3.1) October 14, 2003 40 pages · · · · · · · · · · · · Detailed Description Digitally Controlled Impedance (DCI) Configurable Logic Blocks (CLBs) Sum of Products 3-State Buffers 18-Kb Block SelectRAMTM Resources 18-Bit x 18-Bit Multipliers Global Clock Multiplexer Buffers Digital Clock Manager (DCM) Active Interconnect Technology Creating a Design Configuration
Module 4: Pinout Information
DS031-4 (v2.0) August 1, 2003 225 pages · · Pin Definitions Pinout Tables - CS144 Chip-Scale BGA Package - FG256 Fine-Pitch BGA Package - FG456 Fine-Pitch BGA Package - FG676 Fine-Pitch BGA Package - BG575 Standard BGA Package - BG728 Standard BGA Package - FF896 Flip-Chip Fine-Pitch BGA Package - FF1152 Flip-Chip Fine-Pitch BGA Package - FF1517 Flip-Chip Fine-Pitch BGA Package - BF957Flip-Chip BGA Package
IMPORTANT NOTE: The Virtex-II Platform FPGA data sheet is created and published in separate modules. This complete version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031 October 14, 2003 Product Specification
www.xilinx.com 1-800-255-7778
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VirtexTM-II Platform FPGAs: Introduction and Overview
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DS031-1 (v2.0) August 1, 2003
Product Specification
Summary of Virtex-II Features
· · Industry First Platform FPGA Solution IP-Immersion Architecture - Densities from 40K to 8M system gates - 420 MHz internal clock speed (Advance Data) - 840+ Mb/s I/O (Advance Data) SelectRAMTM Memory Hierarchy - 3 Mb of dual-port RAM in 18 Kbit block SelectRAM resources - Up to 1.5 Mb of distributed SelectRAM resources High-Performance Interfaces to External Memory - DRAM interfaces · SDR / DDR SDRAM · Network FCRAM · Reduced Latency DRAM - SRAM interfaces · SDR / DDR SRAM · QDRTM SRAM - CAM interfaces Arithmetic Functions - Dedicated 18-bit x 18-bit multiplier blocks - Fast look-ahead carry logic chains Flexible Logic Resources - Up to 93,184 internal registers / latches with Clock Enable - Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers - Wide multiplexers and wide-input function support - Horizontal cascade chain and sum-of-products support - Internal 3-state bussing High-Performance Clock Management Circuitry - Up to 12 DCM (Digital Clock Manager) modules · Precise clock de-skew · Flexible frequency synthesis · High-resolution phase shifting - 16 global clock multiplexer buffers Active Interconnect Technology - Four th generation segmented routing structure - Predictable, fast routing delay, independent of fanout SelectIOTM-Ultra Technology - Up to 1,108 user I/Os - 19 single-ended and six differential standards · Programmable sink current (2 mA to 24 mA) per I/O Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards - PCI-X compatible (133 MHz and 66 MHz) at 3.3V - PCI compliant (66 MHz and 33 MHz) at 3.3V - CardBus compliant (33 MHz) at 3.3V - Differential Signaling · 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers · Bus LVDS I/O · Lightning Data Transport (LDT) I/O with current driver buffers · Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O · Built-in DDR input and output registers - Proprietar y high-performance SelectLink Technology · High-bandwidth data path · Double Data Rate (DDR) link · Web-based HDL generation methodology Suppor ted by Xilinx FoundationTM and Alliance SeriesTM Development Systems - Integrated VHDL and Verilog design flows - Compilation of 10M system gates designs - Internet Team Design (ITD) tool SRAM-Based In-System Configuration - Fast SelectMAP configuration - Triple Data Encryption Standard (DES) security option (Bitstream Encryption) - IEEE 1532 support - Par tial reconfiguration - Unlimited reprogrammability - Readback capability 0.15 µm 8-Layer Metal Process with 0.12 µm High-Speed Transistors 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V VCCAUX Auxiliary and VCCO I/O Power Supplies IEEE 1149.1 Compatible Boundary-Scan Logic Support Flip-Chip and Wire-Bond Ball Grid Array (BGA) Packages in Three Standard Fine Pitches (0.80 mm, 1.00 mm, and 1.27 mm) 100% Factory Tested -
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© 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-1 (v2.0) August 1, 2003 Product Specification
www.xilinx.com 1-800-255-7778
Module 1 of 4 1
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VirtexTM-II Platform FPGAs: Introduction and Overview
Table 1: Virtex-II Field-Programmable Gate Array Family Members CLB (1 CLB = 4 slices = Max 128 bits) System Gates 40K 80K 250K 500K 1M 1.5M 2M 3M 4M 6M 8M Array Row x Col. 8x8 16 x 8 24 x 16 32 x 24 40 x 32 48 x 40 56 x 48 64 x 56 80 x 72 96 x 88 112 x 104 Maximum Distributed RAM Kbits 8 16 48 96 160 240 336 448 720 1,056 1,456 M u lt iplie r Blocks 4 8 24 32 40 48 56 96 120 144 168 SelectRAM Blocks 18 Kbit Blocks 4 8 24 32 40 48 56 96 120 144 168 Max RAM (Kbits) 72 144 432 576 720 864 1,008 1,728 2,160 2,592 3,024 Max I/O Pads(1) 88 120 200 264 432 528 624 720 912 1,104 1,108
Device XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000
Slices 256 512 1,536 3,072 5,120 7,680 10,752 14,336 23,040 33,792 46,592
D CM s 4 4 8 8 8 8 8 12 12 12 12
Notes: 1. See details in Table 2, "Maximum Number of User I/O Pads".
General Description
The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces. The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 10 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays. As shown in Table 1, the Virtex-II family comprises 11 members, ranging from 40K to 8M system gates. Table 2 shows the maximum number of user I/Os available. The Virtex-II device/package combination table (Table 6 at the end of this section) details the maximum number of I/Os for each device and package using wire-bond or flip-chip technology. Table 2: Maximum Number of User I/O Pads Device XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 Wire-Bond 88 120 200 264 328 392 516 Flip-Chip 432 528 624 720 912 1,104 1,108
Packaging
Offerings include ball grid array (BGA) packages with 0.80 mm, 1.00 mm, and 1.27 mm pitches. In addition to traditional wire-bond interconnects, flip-chip interconnect is used in some of the BGA offerings. The use of flip-chip interconnect offers more I/Os than is possible in wire-bond versions of the similar packages. Flip-chip construction offers the combination of high pin count with high thermal capacity.
DS031-1 (v2.0) August 1, 2003 Product Specification
www.xilinx.com 1-800-255-7778
Module 1 of 4 2
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