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Details, datasheet, quote on part number:XC2VP30-5FF1704I
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Virtex-II ProTM Platform FPGAs: Complete Data Sheet
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DS083 November 11, 2003
Advance Product Specification
This document includes all four modules of the Virtex-II Pro Platform FPGA data sheet.
Module 1: Introduction and Overview
DS083-1 (v2.4.2) August 25, 2003 8 pages · · · · · · Summary of Features General Description Architecture IP Core and Reference Support Device/Package Combinations and Maximum I/O Ordering Information
Module 3: DC and Switching Characteristics
DS083-3 (v2.12) November 11, 2003 54 pages · · · · · · Electrical Characteristics Performance Characteristics Switching Characteristics Pin-to-Pin Output Parameter Guidelines Pin-to-Pin Input Parameter Guidelines DCM Timing Parameters
Module 2: Functional Description
DS083-2 (v2.9) October 14, 2003 48 pages · · · · Functional Description: RocketIOTM Multi-Gigabit Transceiver Functional Description: Processor Block Functional Description: PowerPCTM 405 Core Functional Description: FPGA - Input/Output Blocks (IOBs) - Digitally Controlled Impedance (DCI) - On-Chip Differential Termination - Configurable Logic Blocks (CLBs) - 3-State Buffers - CLB/Slice Configurations - 18-Kb Block SelectRAMTM Resources - 18-Bit x 18-Bit Multipliers - Global Clock Multiplexer Buffers - Digital Clock Manager (DCM) - Routing - Configuration
Module 4: Pinout Information
DS083-4 (v2.5.5) August 25, 2003 298 pages · · Pin Definitions Pinout Tables - FG256 Wire-Bond Fine-Pitch BGA Package - FG456 Wire-Bond Fine-Pitch BGA Package - FG676 Wire-Bond Fine-Pitch BGA Package - FF672 Flip-Chip Fine-Pitch BGA Package - FF896 Flip-Chip Fine-Pitch BGA Package - FF1148 Flip-Chip Fine-Pitch BGA Package - FF1152 Flip-Chip Fine-Pitch BGA Package - FF1517 Flip-Chip Fine-Pitch BGA Package - FF1696 Flip-Chip Fine-Pitch BGA Package - FF1704 Flip-Chip Fine-Pitch BGA Package
IMPORTANT NOTE: The Virtex-II Pro Platform FPGA data sheet is created and published in separate modules. This complete version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS083 November 11, 2003 Advance Product Specification
www.xilinx.com 1-800-255-7778
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Virtex-II ProTM Platform FPGAs: Introduction and Overview
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DS083-1 (v2.4.2) August 25, 2003
Advance Product Specification
Summary of Virtex-II Pro Features
· High-Performance Platform FPGA Solution, Including - Up to twenty-four RocketIOTM embedded multi-gigabit transceivers - Up to four IBM® PowerPC ® RISC processor blocks Based on VirtexTM-II Platform FPGA Technology - Flexible logic resources - SRAM-based in-system configuration - Active Interconnect technology SelectRAMTM+ memory hierarchy Dedicated 18-bit x 18-bit multiplier blocks High-performance clock management circuitry SelectI/OTM-Ultra technology XCITE Digitally Controlled Impedance (DCI) I/O
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Vir tex-II Pro family members and resources are shown in Table 1.
Table 1: Virtex-II Pro FPGA Family Members
CLB (1 = 4 slices = max 128 bits) Logic Cells(1) 3,168 6,768 11,088 20,880 30,816 43,632 53,136 74,448 99,216 125,136 Slices 1,408 3,008 4,928 9,280 13,696 19,392 23,616 33,088 44,096 55,616 Max Distr RAM (Kb) 44 94 154 290 428 606 738 1,034 1,378 1,738 Block SelectRAM+ 18 Kb Max Block Blocks RAM (Kb) 12 28 44 88 136 192 232 328 444 556 216 504 792 1,584 2,448 3,456 4,176 5,904 7,992 10,008 DCMs 4 4 4 8 8 8 8 8 12 12
Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2VP125
RocketIO Transceiver Blocks 4 4 8 8 8 0(2) or 12 0(2) or 16 16 or 20 0(2) or 20 0(2), 20, or 24
PowerPC Processor Blocks 0 1 1 2 2 2 2 2 2 4
18 X 18 Bit Multiplier Blocks 12 28 44 88 136 192 232 328 444 556
Maximum User I/O Pads 204 348 396 564 644 804 852 996 1,164 1,200
Notes: 1. Logic Cell = (1) 4-input LUT + (1)FF + Carry Logic 2. These devices can be ordered in a configuration without RocketIO transceivers. See Table 3 for package configurations.
RocketIO Transceiver Features
· · · · Full-Duplex Serial Transceiver (SERDES) Capable of Baud Rates from 600 Mb/s to 3.125 Gb/s 120 Gb/s Duplex Data Rate (24 Channels) Monolithic Clock Synthesis and Clock Recovery (CDR) Fibre Channel, 10G Fibre Channel, Gigabit Ethernet, 10 Gb Attachment Unit Interface (XAUI), and Infiniband-Compliant Transceivers 8-, 16-, or 32-bit Selectable Internal FPGA Interface 8B /10B Encoder and Decoder (optional) · · · · · · · · 50 / 75 on-chip Selectable Transmit and Receive Terminations Programmable Comma Detection Channel Bonding Support (from 2 to 24 Channels) Rate Matching via Insertion/Deletion Characters Four Levels of Selectable Pre-Emphasis Five Levels of Output Differential Voltage Per-Channel Internal Loopback Modes 2.5V Transceiver Supply Voltage
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© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS083-1 (v2.4.2) August 25, 2003 Advance Product Specification
www.xilinx.com 1-800-255-7778
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General Description
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PowerPC RISC Block Features
· · · · · · · · Embedded 300+ MHz Harvard Architecture Block Low Power Consumption: 0.9 mW/MHz Five-Stage Data Path Pipeline Hardware Multiply/Divide Unit Thir ty-Two 32-bit General Purpose Registers 16 KB Two-Way Set-Associative Instruction Cache 16 KB Two-Way Set-Associative Data Cache Memory Management Unit (MMU) - 64-entry unified Translation Look-aside Buffers (TLB) - Variable page sizes (1 KB to 16 MB) Dedicated On-Chip Memory (OCM) Interface Suppor ts IBM CoreConnectTM Bus Architecture Debug and Trace Support Timer Facilities ·
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Virtex-II Pro Platform FPGA Technology
· SelectRAM+ Memory Hierarchy - Up to 10 Mb of True Dual-Port RAM in 18 Kb block SelectRAM+ resources - Up to 1,738 Kb of distributed SelectRAM+ resources - High-performance interfaces to external memory Arithmetic Functions - Dedicated 18-bit x 18-bit multiplier blocks - Fast look-ahead carry logic chains Flexible Logic Resources - Up to 111,232 internal registers/latches with Clock Enable - Up to 111,232 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift registers - Wide multiplexers and wide-input function support - Horizontal cascade chain and Sum-of-Products support - Internal 3-state busing High-Performance Clock Management Circuitry - Up to twelve Digital Clock Manager (DCM) modules · Precise clock de-skew · Flexible frequency synthesis · High-resolution phase shifting - 16 global clock multiplexer buffers in all parts Active Interconnect Technology - Four th-generation segmented routing structure - Fast, predictable routing delay, independent of fanout - Deep sub-micron noise immunity benefits SelectIOTM-Ultra Technology - Up to 1,200 user I/Os - Twenty-two single-ended standards and six differential standards
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Programmable LVCMOS sink/source current (2 mA to 24 mA) per I/O - XCITE Digitally Controlled Impedance (DCI) I/O - PCI / PCI-X support (1) - Differential signaling · 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers · Bus LVDS I/O · HyperTranspor t (LDT) I/O with current driver buffers · Built-in DDR input and output registers - Proprietar y high-performance SelectLink technology for communications between Xilinx devices · High-bandwidth data path · Double Data Rate (DDR) link · Web-based HDL generation methodology SRAM-Based In-System Configuration - Fast SelectMAPTM configuration - Triple Data Encryption Standard (DES) security option (bitstream encryption) - IEEE 1532 support - Par tial reconfiguration - Unlimited reprogrammability - Readback capability Suppor ted by Xilinx FoundationTM and Alliance SeriesTM Development Systems - Integrated VHDL and Verilog design flows - ChipScopeTM Integrated Logic Analyzer 0.13 µm Nine-Layer Copper Process with 90 nm High-Speed Transistors 1.5V (VCCINT) core power supply, dedicated 2.5V VCCAUX auxiliary and VCCO I/O power supplies IEEE 1149.1 Compatible Boundary-Scan Logic Support Flip-Chip and Wire-Bond Ball Grid Array (BGA) Packages in Standard 1.00 mm Pitch Each Device 100% Factory Tested
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General Description
The Virtex-II Pro family contains platform FPGAs for designs that are based on IP cores and customized modules. The family incorporates multi-gigabit transceivers and PowerPC CPU blocks in Virtex-II Pro Series FPGA architecture. It empowers complete solutions for telecommunication, wireless, networking, video, and DSP applications. The leading-edge 0.13 µm CMOS nine-layer copper process and Virtex-II Pro architecture are optimized for high performance designs in a wide range of densities. Combining a wide variety of flexible features and IP cores, the Vir tex-II Pro family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gate arrays.
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1. Refer to XAPP653 for more information.
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www.xilinx.com 1-800-255-7778
DS083-1 (v2.4.2) August 25, 2003 Advance Product Specification
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