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Details, datasheet, quote on part number:XC3142A-3TQ144C
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Datasheet text preview:
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XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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November 9, 1998 (Version 3.1)
Product Description · Complete Development System - Schematic capture, automatic place and route - Logic and timing simulation - Interactive design editor for design optimization - Timing calculator - Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others
Features
· Complete line of four related Field Programmable Gate Array product families - XC3000A, XC3000L, XC3100A, XC3100L Ideal for a wide range of custom VLSI design tasks - Replaces TTL, MSI, and other PLD logic - Integrates complete sub-systems into a single package - Avoids the NRE, time delay, and risk of conventional masked gate arrays High-performance CMOS static memory technology - Guaranteed toggle rates of 70 to 370 MHz, logic delays from 7 to 1.5 ns - System clock speeds over 85 MHz - Low quiescent and active power consumption Flexible FPGA architecture - Compatible arrays ranging from 1,000 to 7,500 gate complexity - Extensive register, combinatorial, and I/O capabilities - High fan-out signal distribution, low-skew clock nets - Internal 3-state bus capabilities - TTL or CMOS input thresholds - On-chip crystal oscillator amplifier Unlimited reprogrammability - Easy design iteration - In-system logic changes Extensive packaging options - Over 20 different packages - Plastic and ceramic surface-mount and pin-gridarray packages - Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-tested devices - Excellent reliability record
Device XC3020A, 3020L, 3120A XC3030A, 3030L, 3130A XC3042A, 3042L, 3142A, 3142L XC3064A, 3064L, 3164A XC3090A, 3090L, 3190A, 3190L XC3195A Max Logic Gates 1,500 2,000 3,000 4,500 6,000 7,500 Typical Gate CLBs Range 1,000 - 1,500 64 1,500 - 2,000 2,000 - 3,000 3,500 - 4,500 5,000 - 6,000 6,500 - 7,500 100 144 224 320 484
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Additional XC3100A Features
· Ultra-high-speed FPGA family with six members - 50-85 MHz system clock rates - 190 to 370 MHz guaranteed flip-flop toggle rates - 1.55 to 4.1 ns logic delays High-end additional family member in the 22 X 22 CLB array-size XC3195A device 8 mA output sink current and 8 mA source current Maximum power-down and quiescent current is 5 mA 100% architecture and pin-out compatible with other XC3000 families Software and bitstream compatible with the XC3000, XC3000A, and XC3000L families
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XC3100A combines the features of the XC3000A and XC3100 families: · · · · Additional interconnect resources for TBUFs and CE inputs Error checking of the configuration bitstream Soft startup holds all outputs slew-rate limited during initial power-up More advanced CMOS process
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Low-Voltage Versions Available
· · · Low-voltage devices function at 3.0 - 3.6 V XC3000L - Low-voltage versions of XC3000A devices XC3100L - Low-voltage versions of XC3100A devices
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Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 22 x 22
User I/Os Flip-Flops Max 64 256 80 96 120 144 176 360 480 688 928 1,320
Horizontal Longlines 16 20 24 32 40 44
Configuration Data Bits 14,779 22,176 30,784 46,064 64,160 94,984
November 9, 1998 (Version 3.1)
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XC3000 Series Field Programmable Gate Arrays
Introduction
XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O Blocks (IOBs), a core array of Configurable Logic Bocks (CLBs) and resources for interconnection. The general structure of an FPGA is shown in Figure 2. The development system provides schematic capture and auto place-and-route for design entry. Logic and timing simulation, and in-circuit emulation are available as design verification alternatives. The design editor is used for interactive design optimization, and to compile the data pattern that represents the configuration program. The FPGA user logic functions and interconnections are determined by the configuration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM or ROM on the application circuit board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of program data at power-up. The companion XC17XX Serial Configuration PROMs provide a very simple serial configuration program storage in a one-time programmable package. The XC3000 Field Programmable Gate Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades.
Here is a simple overview of those XC3000 products currently emphasized: · XC3000A Family -- The XC3000A is an enhanced version of the basic XC3000 family, featuring additional interconnect resources and other user-friendly enhancements. XC3000L Family -- The XC3000L is identical in architecture and features to the XC3000A family, but operates at a nominal supply voltage of 3.3 V. The XC3000L is the right solution for battery-operated and low-power applications. XC3100A Family -- The XC3100A is a performance-optimized relative of the XC3000A family. While both families are bitstream and footprint compatible, the XC3100A family extends toggle rates to 370 MHz and in-system performance to over 80 MHz. The XC3100A family also offers one additional array size, the XC3195A. XC3100L Family -- The XC3100L is identical in architectures and features to the XC3100A family, but operates at a nominal supply voltage of 3.3V.
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Figure 1 illustrates the relationships between the families. Compared to the original XC3000 family, XC3000A offers additional functionality and increased speed. The XC3000L family offers the same additional functionality, but reduced speed due to its lower supply voltage of 3.3 V. The XC3100A family offers substantially higher speed and higher density with the XC3195A.
New XC3000 Series Compared to Original XC3000 Family
For readers already familiar with the original XC3000 family of FPGAs, the major new features in the XC3000A, XC3000L, XC3100A, and XC3100L families are listed in this section. All of these new families are upward-compatible extensions of the original XC3000 FPGA architecture. Any bitstream used to configure an XC3000 device will configure the corresponding XC3000A, XC3000L, XC3100A, or XC3100L device exactly the same way. The XC3100A and XC3100L FPGA architectures are upward-compatible extensions of the XC3000A and XC3000L architectures. Any bitstream used to configure an XC3000A or XC3000L device will configure the corresponding XC3100A or XC3100L device exactly the same way.
XC3000 Series Overview
There are now four distinct family groupings within the XC3000 Series of FPGA devices: · · · · XC3000A Family XC3000L Family XC3100A Family XC3100L Family
All four families share a common architecture, development software, design and programming methodology, and also common package pin-outs. An extensive Product Description covers these common aspects. Detailed parametric information for the XC3000A, XC3000L, XC3100A, and XC3100L product families is then provided. (The XC3000 and XC3100 families are not recommended for new designs.)
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XC3000 Series Field Programmable Gate Arrays
Improvements in the XC3000A and XC3000L Families
The XC3000A and XC3000L families offer the following enhancements over the popular XC3000 family: The XC3000A and XC3000L families have additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing. During configuration, the XC3000A and XC3000L devices check the bit-stream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce when all out-puts are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the XC3000 family, determined by the individual configuration option.
(XC3 195A )
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XC310 00L 0 XC310XC31 XC300 0L XC300 0A
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Figure 1: XC3000 FPGA Families
Improvements in the XC3100A and XC3100L Families
Based on a more advanced CMOS process, the XC3100A and XC3100L families are architecturally-identical, performance-optimized relatives of the XC3000A and XC3000L families. While all families are footprint compatible, the XC3100A family extends achievable system performance beyond 85 MHz.
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November 9, 1998 (Version 3.1)
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