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Details, datasheet, quote on part number:XC3S1000-4FG676I
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Spartan-3 1.2V FPGA Family: Complete Data Sheet
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DS099 October 9, 2003
Advance Product Specification
This document includes all four modules of the SpartanTM-3 FPGA data sheet.
Module 1: Introduction and Ordering Information
DS099-1 (v1.1) April 24, 2003 6 pages · · · · · · Introduction Features Architectural Overview Product Availability User I/O Chart Ordering Information
Module 3: DC and Switching Characteristics
DS099-3 (v1.1) July 11, 2003 14 pages · DC Electrical Characteristics - Absolute Maximum Ratings - Recommended Operating Conditions Configuration - Power-On Timing - Timing for the Configuration Modes - Timing for JTAG Port Switching Characteristics - DLL Timing
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Module 2: Functional Description
DS099-2 (v1.2) July 11, 2003 40 pages · IOBs - IOB Overview - SelectIOTM Signal Standards CLB Overview Block RAM Dedicated Multipliers Digital Clock Manager (DCM) - Clock Network Configuration
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Module 4: Pinout Descriptions
DS099-4 (v1.2.2) October 9, 2003 98 pages · · · Pin Descriptions - Pin Behavior During Configuration Package Overview Pinout Tables - Footprints
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IMPORTANT NOTE: The Spartan-3 1.2V FPGA data sheet is created and published in separate modules. This complete version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099 October 9, 2003 Advance Product Specification
www.xilinx.com 1-800-255-7778
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Spartan-3 1.2V FPGA Family: Introduction and Ordering Information
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DS099-1 (v1.1) April 24, 2003
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Advance Product Specification Densities as high as 74,880 logic cells 326 MHz system clock rate Three separate power supplies for the core (1.2V), I/Os (1.2V to 3.3V), and special functions (2.5V) SelectIOTM signaling - Up to 784 I/O pins - 622 Mb/s data transfer rate per I/O - Seventeen single-ended signal standards - Six differential signal standards including LVDS - Termination by Digitally Controlled Impedance - Signal swing ranging from 1.14V to 3.45V - Double Data Rate (DDR) support Logic resources - Abundant, flexible logic cells with registers - Wide multiplexers - Fast look-ahead carry logic - Dedicated 18 x 18 multipliers - JTAG logic compatible with IEEE 1149.1/1532 standards SelectRAMTM hierarchical memory - Up to 1,872 Kbits of total block RAM - Up to 520 Kbits of total distributed RAM Digital Clock Manager (up to four DCMs) - Clock skew elimination - Frequency synthesis - High resolution phase shifting Eight global clock lines and abundant routing Fully supported by Xilinx ISE development system - Synthesis, mapping, placement and routing -
Introduction
The 1.2V SpartanTM-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to five million system gates, as shown in Table 1. The Spartan-3 family builds on the success of the earlier Spar tan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from state-of-the-art VirtexTM-II technology. These Spartan-3 enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment. The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.
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Features
· · Revolutionary 90-nanometer process technology Very low cost, high-performance logic solution for high-volume, consumer-oriented applications
CLB Array (One CLB = Four Slices) Rows 16 24 32 48 64 80 96 104 Columns Total CLBs 12 20 28 40 52 64 72 80 192 480 896 1, 920 3, 328 5, 120 6, 912 8, 320
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Table 1: Summary of Spartan-3 FPGA Attributes
Syst em Gates 50K 200K 400K 1M 1. 5M 2M 4M 5M Logic Cells 1,728 4,320 8,064 17, 280 29, 952 46, 080 62, 208 74, 880 Distributed RAM (bits1) 12K 30K 56K 1 20K 2 08K 3 20K 4 32K 5 20K Block RAM (bits1) 72 K 216K 288K 432K 576K 720K 1, 728K 1, 872K Dedicated Multipliers 4 12 16 24 32 40 96 104 Maximum User I/O 12 4 17 3 26 4 39 1 48 7 56 5 71 2 78 4 Maximum Differential I/O Pairs 56 76 116 175 221 270 312 344
Device XC3S50 XC3S 200 XC3S 400 XC3S 1000 XC3S 1500 XC3S 2000 XC3S 4000 XC3S 5000
DCM s 2 4 4 4 4 4 4 4
No tes: 1. By convention, one Kb is equivalent to 1,024 bits.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099-1 (v1.1) April 24, 2003 Advance Product Specification
www.xilinx.com 1-800-255-7778
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Spartan-3 1.2V FPGA Family: Introduction and Ordering Information
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Architectural Overview
The Spartan-3 family architecture consists of five fundamental programmable functional elements: · Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical functions as well as to store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Twenty-three different signal standards, including six high-performance differential standards, are available as shown in Table 2. Double Data-Rate (DDR) registers are included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying board designs. Block RAM provides data storage in the form of 18-Kbit dual-por t blocks. Multiplier blocks accept two 18-bit binary numbers as · inputs and calculate the product. Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals.
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These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. The XC3S50 has a single column of block RAM embedded in the array. Those devices ranging from the XC3S200 to the XC3S2000 have two columns of block RAM. The XC3S4000 and XC3S5000 devices have four RAM columns. Each column is made up of several 18K-bit RAM blocks; each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of each block RAM column. The Spartan-3 family features a rich network of traces and switches that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing.
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DS099-1_01_032703
Notes: 1. The two additional block RAM columns of the XC3S4000 and XC3S5000 devices are shown with dashed lines. The XC3S50 has only the block RAM column on the far left.
Figure 1: Spartan-3 Family Architecture
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DS099-1 (v1.1) April 24, 2003 Advance Product Specification
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