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Details, datasheet, quote on part number:XC4013XLA-7PQ240C
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XC4000XLA/XV Field Programmable Gate Arrays
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DS015 (v1.3) October 18, 1999
Product Specification
XC4000XLA/XV Family Features
Note: XC4000XLA devices are improved versions of XC4000XL devices. The XC4000XV devices have the same features as XLA devices, incor porate additional interconnect resources and extend gate capacity to 500,000 system gates. The XC4000XV devices require a separate 2.5V power supply for internal logic but maintain 5V I/O compatibility via a separate 3.3V I/O power supply. For additional information about the XC4000XLA/XV device architecture, refer to the XC4000E/X FPGA Series general and functional descriptions. · System-featured Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with - Synchronous write option - Dual-por t RAM option - Flexible function generators and abundant flip-flops - Dedicated high-speed carry logic - Internal 3-state bus capability - Eight global low-skew clock or signal distribution networks · Flexible Array Architecture · Low-power Segmented Routing Architecture · Systems-oriented Features - IEEE 1149.1-compatible boundary scan - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - Unlimited reprogrammability · Read Back Capability - Program verification and internal node observability
Table 1: XC4000XLA Series Field Programmable Gate Arrays
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Electrical Features
· XLA Devices Require 3.0 - 3.6 V (VCC) · XV Devices Require 2.3- 2.7 V (VCCINT) and 3.0 - 3.6 V (VCCIO) · 5.0 V TTL compatible I/O · 3.3 V LVTTL, LVCMOS compliant I/O · 5.0 V and 3.0 V PCI Compliant I/O · 12 mA or 24 mA Current Sink Capability · Safe under All Power-up Sequences · XLA Consumes 40% Less Power than XL · XV Consumes 65% Less Power than XL · Optional Input Clamping to VCC (XLA) or VCCIO (XV)
Additional Features
· Footprint Compatible with XC4000XL FPGAs - Lower cost with improved performance and lower power · Advanced Technology -- 5 layer metal, 0.25 µm CMOS process (XV) or 0.35 µm CMOS process (XLA) · Highest Performance -- System erformance beyond 100 MHz · High Capacity -- Up to 500,000 system gates and 270,000 synchronous SRAM bits · Low Power -- 3.3 V/2.5 V technology plus segmented routing architecture · Safe and Easy to Use -- Interfaces to any combination of 3.3 V and 5.0 V TTL compatible devices
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Device XC4013XLA XC4020XLA XC4028XLA XC4036XLA XC4044XLA XC4052XLA XC4062XLA XC4085XLA XC40110XV XC40150XV XC40200XV XC40250XV
Logic Cells 1,368 1,862 2,432 3,078 3,800 4,598 5,472 7,448 9,728 12,312 16,758 20,102
Max Logic Max. RAM Typical Gates Bits Gate Range (No RAM) (No Logic) (Logic and RAM)* 13,000 20,000 28,000 36,000 44,000 52,000 62,000 85,000 110,000 150,000 200,000 250,000 18,432 25,088 32,768 41,472 51,200 61,952 73,728 100,352 131,072 165,888 225,792 270,848 10,000 - 30,000 13,000 - 40,000 18,000 - 50,000 22,000 - 65,000 27,000 - 80,000 33,000 - 100,000 40,000 - 130,000 55,000 - 180,000 75,000 - 235,000 100,000 - 300,000 130,000 - 400,000 180,000 - 500,000
CLB Matrix 24 x 24 28 x 28 32 x 32 36 x 36 40 x 40 44 x 44 48 x 48 56 x 56 64 x 64 72 x 72 84 x 84 92 x 92
Total CLBs 576 784 1,024 1,296 1,600 1,936 2,304 3,136 4,096 5,184 7,056 8,464
Number of Flip-Flops 1,536 2,016 2,560 3,168 3,840 4,576 5,376 7,168 9,216 11,520 15,456 18,400
Required Max. ConfigurUser I/O ation Bits 192 224 256 288 320 352 384 448 448 448 448 448 393,632 521,880 668,184 832,528 1,014,928 1,215,368 1,433,864 1,924,992 2,686,136 3,373,448 4,551,056 5,433,888
* Maximum values of gate range assume 20-30% of CLBs used as RAM
DS015 (v1.3) October 18, 1999 - Product Specification
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XC4000XLA/XV Field Programmable Gate Arrays
The XV devices also incorporate additional routing resources in the form of 8 octal-length segmented routing channels vertically and horizontally per row and column.
General Description
XC4000 Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of fifteen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs.
XLA/XV and XL Family Differences
The XC4000XLA/XV families of FPGAs are logically identical to XC4000EX and XC4000XL FPGAs, however I/O, configuration logic, JTAG functionality, and performance have been enhanced. In addition, they deliver: · Improved Performance XLA/XV devices benefit from advance processing technology and a reduction in interconnect capacitance which improves performance over XL devices by more than 30%. · Lower Power XLA/XV devices have reduced power requirements compared to equivalent XL devices. · Shorter routing delays The smaller die of XLA/XV devices directly reduces clock delays and the delay of high-fanout signals. The reduction in clock delay allows improved pin-to-pin I/O specifications. · Lower Cost XLA/XV device cost is directly related to the die size and has been reduced significantly from that of equivalent XL devices. · Express mode configuration Express mode configuration is available on the XLA and XV devices.
Figure 1: Cross Section of Xilinx 0.25 micron, 5 layer metal XC4000XV FPGA. Visible features are five layers of metallization, tungsten plug vias and trench isolation. The small gaps above the lowest layer are 0.25 micron polysilicon MOSFET gates. The excellent planarity of each metal layer is due to the use of "chemical-mechanical polishing" or CMP. In effect, each layer is ground flat before a new layer is added.
IOB Enhancements
· 12/24 mA Output Drive The XLA/XV family of FPGAs allow individual IOBs to be configured as high drive outputs. Each output can be configured to have 24 mA drive strength as opposed to the standard default strength of 12 mA. · VCC Clamping Diode XLA and XV FPGAs have an optional clamping diode connected from each output to VCC (VCCIO for XV). When enabled they clamp ringing transients back to the 3.3V supply rail. This clamping action is required in 3.3V PCI applications. VCC clamping is a global option affecting all I/O pins. If enabled, TTL I/O compatibility is maintained, but full 5.0 Volt I/O tolerance is sacrificed. · Enhanced ESD protection An improved ESD structure allows XV devices to safely pass the stringent 5V PCI (4.2.1.3) ringing test. This test applies an 11V pulse to each IOB for 11 ns via a 55 ohm resistor. · Full 3.3V and 5.0V PCI compliance The addition of 12/24 mA drive, optional 3.3V clamping and improved ESD provides full compliance with either 3.3V or 5.0V PCI specifications.
Technology Advantage
XC4000XLA/XV FPGAs use 5 layer metal silicon technology to improve performance while reducing device cost and power. In addition, IOB enhancements provide full PCI compliance and the JTAG functionality is expanded.
Low Power Internal Logic
XC4000XV FPGAs incorporate all the features of the XLA devices but require a separate 2.5V power supply for internal logic. I/O pads are still driven from a 3.3V power supply. The 2.5V logic supply is named VCCINT and the 3.3 V IO supply is named VCCIO.
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DS015 (v1.3) October 18, 1999 - Product Specification
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XC4000XLA/XV Field Programmable Gate Arrays
Three-State Register
XC4000XLA/XV devices incorporate an optional register controlling the three-state enable in the IOBs.The use of the three-state control register can significantly improve output enable and disable time.
Table 2: K-Factor and Relative Power. Power Power Relative To Relative To XL XLA 1.00 1.65 0.60 1.00 0.35 0.58
FastCLK Clock Buffers
The XLA/XV devices incorporate FastCLK clock buffers. Two FastCLK buffers are available on each of the right and left edges of the die. Each FastCLK buffer can provide a fast clock signal (typically < 1.5 ns clock delay) to all the IOBs within the IOB octant containing the buffer. The FastCLK buffers can be instantiated by use of the BUFFCLK symbols. (In addition to FastCLK buffers, the Global Early BUFGE clock buffers #1, #2, #5, and #6 can also provide fast clock signals (typically < 1.5 ns clock delay) to IOBs on the top and bottom of the die.
FPGA Family XC4000XL XC4000XLA XC4000XV
K-Factor 28 17 13
XLA/XV Logic Performance
XC4000XLA/XV devices feature 30% faster device speed than XL devices, and consistent performance is achieved across all family members. Table 3 illustrates the performance of the XLA devices. For details regarding the implementation of these benchmarks refer to XBRF15 "Speed Metrics for High Performance FPGAs". Table 3: XLA/XV Estimated Benchmark Performance Register - Register Benchmarks Adder 2 Cascaded Adders 4 Cascaded Adders Size 8-Bit 16-Bit 32-Bit 16-Bit 16-Bit 1 Level 2 Level 4 Level 6 Level 1 CLBs 4 CLBs 16 CLBs 64 CLBs 128 CLBs 8-Bits by 16 8-Bits by 256 Maximum Frequency 172 MHz 144 MHz 108 MHz 94 MHz 57 MHz 314 MHz 193 MHz 108 MHz 75 MHz 325 MHz 260 MHz 185 MHz 108 MHz 81 MHz 172 MHz 172 MHz
XLA/XV Power Requirements
XC4000XLA devices require 40% less power per CLB than equivalent XL devices. XC4000XV devices require 42% less power per CLB than equivalent XLA devices and 65% less power than XL devices The representative K-Factor for the following families can be found in Table 2. The K-Factor predicts device current for typical user designs and is based on filling the FPGA with active 16-Bit counters and measuring the device current at 1 MHz. This technique is described in XBRF14 "A Simple Method of Estimating Power in XC4000XL/EX/E FPGAs". To predict device power (P) using the K-Factor use the following formula: P=V*K*N*F; where: P= Device Power V= Power supply voltage K= the Device K-Factor N = number of active registers F = Frequency in MHz
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Cascaded 4LUTs
Interconnect (Manhattan Distance)
Dual Port RAM (Pipelined)
DS015 (v1.3) October 18, 1999 - Product Specification
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