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Part: XC4020XL-3BG256I
Category:
FPGAs/PLDs
-> FPGA (Field Programmable Gate Array)
Description: XC4000 Field Programmable Gate Array
Company: Xilinx Corp.
Datasheet: Download XC4020XL-3BG256I datasheet File size : 3 kB
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XC4000E and XC4000X Series Field Programmable Gate Arrays
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May 14, 1999 (Version 1.6)
Product Specification
XC4000E and XC4000X Series Features
Note: Information in this data sheet covers the XC4000E, XC4000EX, and XC4000XL families. A separate data sheet covers the XC4000XLA and XC4000XV families. Electrical Specifications and package/pin information are covered in separate sections for each family to make the information easier to access, review, and print. For access to these sections, see the Xilinx web site at http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp · System featured Field-Programmable Gate Arrays - SelectRAMTM memory: on-chip ultra-fast RAM with - synchronous write option - dual-por t RAM option - Fully PCI compliant (speed grades -2 and faster) - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - Eight global low-skew clock or signal distribution networks · System Performance beyond 80 MHz · Flexible Array Architecture · Low Power Segmented Routing Architecture · Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic suppor t - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12 mA sink current per XC4000E output · Configured by Loading Binary File - Unlimited re-programmability · Read Back Capability - Program verification - Internal node observability · Backward Compatible with XC4000 Devices · Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization
Low-Voltage Versions Available
· Low-Voltage Devices Function at 3.0 - 3.6 Volts · XC4000XL: High Performance Low-Voltage Versions of XC4000EX devices
Additional XC4000X Series Features
· · · · · High Performance -- 3.3 V XC4000XL High Capacity -- Over 180,000 Usable Gates 5 V tolerant I/Os on XC4000XL 0.35 µm SRAM process for XC4000XL Additional Routing Over XC4000E - almost twice the routing capacity for high-density designs Buffered Interconnect for Maximum Speed Blocks Improved VersaRingTM I/O Interconnect for Better Fixed Pinout Flexibility 12 mA Sink Current Per XC4000X Output Flexible New High-Speed Clock Network - Eight additional Early Buffers for shor ter clock delays - Vir tually unlimited number of clock signals Optional Multiplexer or 2-input Function Generator on Device Outputs Four Additional Address Bits in Master Parallel Configuration Mode 0
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Introduction
XC4000 Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thir teen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-por t modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs. The XC4000E and XC4000X Series currently have 20 members, as shown in Table 1.
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XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000E and XC4000X Series Compared to the XC4000
For readers already familiar with the XC4000 family of Xilinx Field Programmable Gate Arrays, the major new features in the XC4000 Series devices are listed in this section. The biggest advantages of XC4000E and XC4000X devices are significantly increased system speed, greater capacity, and new architectural features, par ticularly Select-RAM memory. The XC4000X devices also offer many new routing features, including special high-speed clock buffers that can be used to capture input data with minimal delay. Any XC4000E device is pinout- and bitstream-compatible with the corresponding XC4000 device. An existing XC4000 bitstream can be used to program an XC4000E device. However, since the XC4000E includes many new features, an XC4000E bitstream cannot be loaded into an XC4000 device. XC4000X Series devices are not bitstream-compatible with equivalent array size devices in the XC4000 or XC4000E families. However, equivalent array size devices, such as the XC4025, XC4025E, XC4028EX, and XC4028XL, are pinout-compatible.
much as 50% from XC4000 values. See "Fast Carr y Logic" on page 18 for more information.
Select-RAM Memory: Edge-Triggered, Synchronous RAM Modes
The RAM in any CLB can be configured for synchronous, edge-triggered, write operation. The read operation is not affected by this change to an edge-triggered write.
Dual-Port RAM
A separate option conver ts the 16x2 RAM in any CLB into a 16x1 dual-port RAM with simultaneous Read/Write. The function generators in each CLB can be configured as either level-sensitive (asynchronous) single-por t RAM, edge-triggered (synchronous) single-por t RAM, edge-triggered (synchronous) dual-por t RAM, or as combinatorial logic.
Configurable RAM Content
The RAM content can now be loaded at configuration time, so that the RAM starts up with user-defined data.
H Function Generator
In current XC4000 Series devices, the H function generator is more versatile than in the original XC4000. Its inputs can come not only from the F and G function generators but also from up to three of the four control input lines. The H function generator can thus be totally or par tially independent of the other two function generators, increasing the maximum capacity of the device.
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Improvements in XC4000E and XC4000X
Increased System Speed
XC4000E and XC4000X devices can run at synchronous system clock rates of up to 80 MHz, and internal performance can exceed 150 MHz. This increase in performance over the previous families stems from improvements in both device processing and system architecture. XC4000 Series devices use a sub-micron multi-layer metal process. In addition, many architectural improvements have been made, as described below. The XC4000XL family is a high performance 3.3V family based on 0.35µ SRAM technology and suppor ts system speeds to 80 MHz.
IOB Clock Enable
The two flip-flops in each IOB have a common clock enable input, which through configuration can be activated individually for the input or output flip-flop or both. This clock enable operates exactly like the EC pin on the XC4000 CLB. This new feature makes the IOBs more versatile, and avoids the need for clock gating.
Output Drivers
The output pull-up structure defaults to a TTL-like totem-pole. This driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below Vcc, just like the XC4000 family outputs. Alternatively, XC4000 Series devices can be globally configured with CMOS outputs, with p-channel pull-up transistors pulling to Vcc. Also, the configurable pull-up resistor in the XC4000 Series is a p-channel transistor that pulls to Vcc, whereas in the original XC4000 family it is an n-channel transistor that pulls to a voltage one transistor threshold below Vcc.
PCI Compliance
XC4000 Series -2 and faster speed grades are fully PCI compliant. XC4000E and XC4000X devices can be used to implement a one-chip PCI solution.
Carry Logic
The speed of the carry logic chain has increased dramatically. Some parameters, such as the delay on the carry chain through a single CLB (TBYP), have improved by as
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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays Logic Cells 152 238 466 608 770 950 1368 1862 2432 2432 3078 3800 4598 5472 7448 Max Logic Max. RAM Gates Bits (No RAM) (No Logic) 1,600 2,048 3,000 3,200 5,000 6,272 6,000 8,192 8,000 10,368 10,000 12,800 13,000 18,432 20,000 25,088 25,000 32,768 28,000 32,768 36,000 41,472 44,000 51,200 52,000 61,952 62,000 73,728 85,000 100,352 Typical Gate Range (Logic and RAM)* 1,000 - 3,000 2,000 - 5,000 3,000 - 9,000 4,000 - 12,000 6,000 - 15,000 7,000 - 20,000 10,000 - 30,000 13,000 - 40,000 15,000 - 45,000 18,000 - 50,000 22,000 - 65,000 27,000 - 80,000 33,000 - 100,000 40,000 - 130,000 55,000 - 180,000 CLB Matrix 8x8 10 x 10 14 x 14 16 x 16 18 x 18 20 x 20 24 x 24 28 x 28 32 x 32 32 x 32 36 x 36 40 x 40 44 x 44 48 x 48 56 x 56 Total CLBs 64 100 196 256 324 400 576 784 1,024 1,024 1,296 1,600 1,936 2,304 3,136 Number of Max. Flip-Flops User I/O 256 64 360 80 616 112 768 128 936 144 1,120 160 1,536 192 2,016 224 2,560 256 2,560 256 3,168 288 3,840 320 4,576 352 5,376 384 7,168 448
Device XC4002XL XC4003E XC4005E/XL XC4006E XC4008E XC4010E/XL XC4013E/XL XC4020E/XL XC4025E XC4028EX/XL XC4036EX/XL XC4044XL XC4052XL XC4062XL XC4085XL
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Note: All functionality in low-voltage families is the same as in the corresponding 5-Volt family, except where numerical references are made to timing or power.
Description
XC4000 Series devices are implemented with a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs). They have generous routing resources to accommodate the most complex interconnect patterns. The devices are customized by loading configuration data into internal memor y cells. The FPGA can either actively read its configuration data from an external serial or byte-parallel PROM (master modes), or the configuration data can be written into the FPGA from an external device (slave and peripheral modes). XC4000 Series FPGAs are suppor ted by powerful and sophisticated software, covering ever y aspect of design from schematic or behavioral entr y, floor planning, simulation, automatic block placement and routing of interconnects, to the creation, downloading, and readback of the configuration bit stream. Because Xilinx FPGAs can be reprogrammed an unlimited number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hardware must be adapted to different user applications. FPGAs are ideal for shor tening design and development cycles, and also offer a cost-effective solution for production rates well beyond 5,000 systems per month. n ' .
Taking Advantage of Re-configuration
FPGA devices can be re-configured to change logic function while resident in the system. This capability gives the system designer a new degree of freedom not available with any other type of logic. Hardware can be changed as easily as software. Design updates or modifications are easy, and can be made to products already in the field. An FPGA can even be re-configured dynamically to perform different functions at different times. Re-configurable logic can be used to implement system self-diagnostics, create systems capable of being re-configured for different environments or operations, or implement multi-pur pose hardware for a given application. As an added benefit, using re-configurable FPGA devices simplifies hardware design and debugging and shor tens product time-to-market.
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May 14, 1999 (Version 1.6)
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