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Details, datasheet, quote on part number:XC5206-6
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XC5200 Series Field Programmable Gate Arrays
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November 5, 1998 (Version 5.2)
Product Specification Footprint compatibility in common packages within the XC5200 Series and with the XC4000 Series - Over 150 device/package combinations, including advanced BGA, TQ, and VQ packaging available Fully Supported by Xilinx Development System - Automatic place and route software - Wide selection of PC and Workstation platforms - Over 100 3rd-party Alliance interfaces - Supported by shrink-wrap Foundation software
Features
· Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 "gates") - Price competitive with Gate Arrays · System Level Features - System performance beyond 50 MHz - 6 levels of interconnect hierarchy - VersaRingTM I/O Interface for pin-locking - Dedicated carry logic for high-speed arithmetic functions - Cascade chain for wide input functions - Built-in IEEE 1149.1 JTAG boundary scan test circuitry on all I/O pins - Internal 3-state bussing capability - Four dedicated low-skew clock or signal distribution nets · Versatile I/O and Packaging - Innovative VersaRingTM I/O interface provides a high logic cell to I/O ratio, with up to 244 I/O signals - Programmable output slew-rate control maximizes performance and reduces noise - Zero Flip-Flop hold time for input registers simplifies system timing - Independent Output Enables for external bussing ·
Description
The XC5200 Field-Programmable Gate Array Family is engineered to deliver low cost. Building on experiences gained with three previous successful SRAM FPGA families, the XC5200 family brings a robust feature set to programmable logic design. The VersaBlockTM logic module, the VersaRing I/O interface, and a rich hierarchy of interconnect resources combine to enhance design flexibility and reduce time-to-market. Complete support for the XC5200 family is delivered through the familiar Xilinx software environment. The XC5200 family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, VHDL, and Verilog HDL synthesis. Designers utilizing logic synthesis can use their existing tools to design with the XC5200 devices.
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Table 1: XC5200 Field-Programmable Gate Array Family Members Device Logic Cells Max Logic Gates Typical Gate Range VersaBlock Array CL B s Flip-Flops I/Os TBUFs per Longline XC5202 256 3,000 2,000 - 3,000 8x8 64 256 84 10 XC5204 480 6,000 4,000 - 6,000 10 x 12 120 480 124 14 XC5206 784 10,000 6,000 - 10,000 14 x 14 196 784 148 16 XC5210 1,296 16,000 XC5215 1,936 23,000
10,000 - 16,000 15,000 - 23,000 18 x 18 324 1,296 196 20 22 x 22 484 1,936 244 24
November 5, 1998 (Version 5.2)
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XC5200 Series Field Programmable Gate Arrays
XC5200 Family Compared to XC4000/SpartanTM and XC3000 Series
For readers already familiar with the XC4000/Spartan and XC3000 FPGA Families, this section describes significant differences between them and the XC5200 family. Unless otherwise indicated, comparisons refer to both XC4000/Spartan and XC3000 devices.
Table 2: Xilinx Field-Programmable Gate Array Families Parameter CLB function generators CLB inputs CLB outputs Global buffers User RAM Edge decoders Cascade chain Fast carry logic Internal 3-state Boundary scan Slew-rate control XC5200 Spartan XC4000 XC3000 4 20 12 4 no no yes yes yes yes yes 3 9 4 8 yes no no yes yes yes yes 3 9 4 8 yes yes no yes yes yes yes 2 5 2 2 no no no no yes no yes
Configurable Logic Block (CLB) Resources
Each XC5200 CLB contains four independent 4-input function generators and four registers, which are configured as four independent Logic CellsTM (LCs). The registers in each XC5200 LC are optionally configurable as edge-triggered D-type flip-flops or as transparent level-sensitive latches. The XC5200 CLB includes dedicated carry logic that provides fast arithmetic carry capability. The dedicated carry logic may also be used to cascade function generators for implementing wide arithmetic functions.
XC4000 family: XC5200 devices have no wide edge decoders. Wide decoders are implemented using cascade logic. Although sacrificing speed for some designs, lack of wide edge decoders reduces the die area and hence cost of the XC5200. XC4000/Spartan family: XC5200 dedicated carry logic differs from that of the XC4000/Spartan family in that the sum is generated in an additional function generator in the adjacent column. This design reduces XC5200 die size and hence cost for many applications. Note, however, that a loadable up/down counter requires the same number of function generators in both families. XC3000 has no dedicated carry. XC4000/Spartan family: XC5200 lookup tables are optimized for cost and hence cannot implement RAM.
Routing Resources
The XC5200 family provides a flexible coupling of logic and local routing resources called the VersaBlock. The XC5200 VersaBlock element includes the CLB, a Local Interconnect Matrix (LIM), and direct connects to neighboring VersaBlocks. The XC5200 provides four global buffers for clocking or high-fanout control signals. Each buffer may be sourced by means of its dedicated pad or from any internal source. Each XC5200 TBUF can drive up to two horizontal and two vertical Longlines. There are no internal pull-ups for XC5200 Longlines.
Input/Output Block (IOB) Resources
The XC5200 family maintains footprint compatibility with the XC4000 family, but not with the XC3000 family. To minimize cost and maximize the number of I/O per Logic Cell, the XC5200 I/O does not include flip-flops or latches. For high performance paths, the XC5200 family provides direct connections from each IOB to the registers in the adjacent CLB in order to emulate IOB registers. Each XC5200 I/O Pin provides a programmable delay element to control input set-up time. This element can be used to avoid potential hold-time problems. Each XC5200 I/O Pin is capable of 8-mA source and sink currents. IEEE 1149.1-type boundary scan is supported in each XC5200 I/O.
Configuration and Readback
The XC5200 supports a new configuration mode called Express mode.
XC4000/Spartan family: The XC5200 family provides a global reset but not a global set.
XC5200 devices use a different configuration process than that of the XC3000 family, but use the same process as the XC4000 and Spartan families.
XC3000 family: Although their configuration processes differ, XC5200 devices may be used in daisy chains with XC3000 devices. XC3000 family: The XC5200 PROGRAM pin is a single-function input pin that overrides all other inputs. The PROGRAM pin does not exist in XC3000.
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XC5200 Series Field Programmable Gate Arrays
XC3000 family: XC5200 devices support an additional programming mode: Peripheral Synchronous. XC3000 family: The XC5200 family does not support Power-down, but offers a Global 3-state input that does not reset any flip-flops. XC3000 family: The XC5200 family does not provide an on-chip crystal oscillator amplifier, but it does provide an internal oscillator from which a variety of frequencies up to 12 MHz are available.
VersaRing GRM VersaBlock Input/Output Blocks (IOBs)
VersaRing GRM VersaBlock GRM VersaBlock
Architectural Overview
Figure 1 presents a simplified, conceptual overview of the XC5200 architecture. Similar to conventional FPGAs, the XC5200 family consists of programmable IOBs, programmable logic blocks, and programmable interconnect. Unlike other FPGAs, however, the logic and local routing resources of the XC5200 family are combined in flexible VersaBlocks (Figure 2). General-purpose routing connects to the VersaBlock through the General Routing Matrix (GRM).
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
VersaRing
VersaRing
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Figure 1: XC5200 Architectural Overview
VersaBlock: Abundant Local Routing Plus Versatile Logic
GRM
The basic logic element in each VersaBlock structure is the Logic Cell, shown in Figure 3. Each LC contains a 4-input function generator (F), a storage device (FD), and control logic. There are five independent inputs and three outputs to each LC. The independence of the inputs and outputs allows the software to maximize the resource utilization within each LC. Each Logic Cell also contains a direct feedthrough path that does not sacrifice the use of either the function generator or the register; this feature is a first for FPGAs. The storage device is configurable as either a D flip-flop or a latch. The control logic consists of carry logic for fast implementation of arithmetic functions, which can also be configured as a cascade chain allowing decode of very wide input functions.
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CLB
LC3
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LC2 LC1 LC0
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LIM
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Direct Connects
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Figure 2: VersaBlock
CO DO DI D F4 F3 F2 F1 X CI CE CK CLR
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FD F
Figure 3: XC5200 Logic Cell (Four LCs per CLB)
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