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Details, datasheet, quote on part number:XC95144-7
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XC9500 In-System Programmable CPLD Family
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DS063 (v5.1) September 22, 2003
Product Specification Advanced CMOS 5V Fast FLASHTM technology Suppor ts parallel programming of multiple XC9500 devices
Features
· High-perfor mance · · 5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 36 to 288 macrocells with 800 to 6,400 usable gates Endurance of 10,000 program/erase cycles Program/erase over full commercial voltage and temperature range
Family Overview
The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan suppor t is also included on all family members. As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 to 288 registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in a given package footprint. The XC9500 architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. An expanded JTAG instr uction set allows version control of programming patter ns and in-system debugging. In-system programming throughout the full device operating range and a minimum of 10,000 program/erase cycles provide worry-free reconfigurations and system field upgrades. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. I/Os may be configured for 3.3V or 5V operation. All outputs provide 24 mA drive.
Large density range
5V in-system programmable -
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Enhanced pin-locking architecture Flexible 36V18 Function Block 90 product terms drive any or all of 18 macrocells within Function Block Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-dr ive 24 mA outputs 3.3V or 5V I/O capability
Table 1: XC9500 Device Family X C 9536 Macrocells Usable Gates Registers TPD (ns) TSU (ns) TCO (ns) fCNT (MHz)(1) fSYSTEM (MHz)(2) 36 8 00 36 5 3. 5 4. 0 1 00 1 00 X C 95 72 72 1,600 72 7.5 4.5 4.5 125 83. 3 X C 95 108 108 2, 400 108 7.5 4.5 4.5 125 83. 3 X C 9514 4 144 3, 200 144 7. 5 4. 5 4. 5 125 83.3 XC 95216 216 4,800 216 10 6.0 6.0 111.1 66. 7 X C 952 88 2 88 6, 400 2 88 15 8. 0 8. 0 92.2 56.6
Notes: 1. fCNT = Operating frequency for 16-bit counters. 2. fSYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS063 (v5.1) September 22, 2003 Product Specification
www.xilinx.com 1-800-255-7778
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XC9500 In-System Programmable CPLD Family Table 2: Available Packages and Device I/O Pins (not including dedicated JTAG pins) X C 9536 44-Pin VQFP 44-Pin PLCC 48-Pin CSP 84-Pin PLCC 100-Pin TQFP 100-Pin PQFP 160-Pin PQFP 208-Pin HQFP 352-Pin BGA 34 34 34 X C 9572 34 69 72 72 X C 95108 69 81 81 108 X C 9514 4 81 81 133 X C95 216 1 33 1 66 1 66 XC 95288 168 192
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Architecture Description
Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the Fast CONNECTTM switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with 36 inputs and
3 JTAG Port JTAG Controller
18 outputs. The Fast C ONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs. See Figure 1.
In-System Programming Controller
36 I/O I/O I/O Fast CONNECT II Switch Matrix I/O 36 18 18
Function Block 1 Macrocells 1 to 18
Function Block 2 Macrocells 1 to 18
I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2 or 4
36 18
Function Block 3 Macrocells 1 to 18
36 18
Function Block N Macrocells 1 to 18
DS063_01_110501
Figure 1: XC9500 Architecture Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly.
2 www.xilinx.com 1-800-255-7778 D S063 (v5.1) September 22, 2003 Product Specification
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XC9500 In-System Programmable CPLD Family
Function Block
Each Function Block, as shown in Figure 2, is comprised of 18 independent macrocells, each capable of implementing a combinatorial or registered function. The FB also receives global clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the Fast CONNECT switch matr ix. These 18 outputs and their corresponding output enable signals also drive the IOB. Logic within the FB is implemented using a sum-of-products representation. Thirty-six inputs provide 72 true and complement signals into the programmable AND-array to form 90 product terms. Any number of these product terms, up to the 90 available, can be allocated to each macrocell by the product term allocator. Each FB (except for the XC9536) supports local feedback paths that allow any number of FB outputs to drive into its own programmable AND-array without going outside the FB. These paths are used for creating very fast counters and state machines where all state registers are within the same FB.
Macrocell 1
Programmable AND-Array From Fast CONNECT II Switch Matrix
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Product Term Allocators
18 18 18
To Fast CONNECT II Switch Matrix OUT To I/O Blocks PTOE
Macrocell 18
1 3
Global Global Set/Reset Clocks
DS063_02_110501
Figure 2: XC9500 Function Block
DS063 (v5.1) September 22, 2003 Product Specification
www.xilinx.com 1-800-255-7778
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