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Details, datasheet, quote on part number:XC95144XL-5TQ100C
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XC9500XL High-Performance CPLD Family
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DS054 (v1.6) January 24, 2002
Preliminary Product Specification · Individual output enable per output pin with local inversion Input hysteresis on all user and boundary-scan pin inputs Bus-hold circuitry on all user pin inputs Suppor ts hot-plugging capability Full IEEE Standard 1149.1 boundary-scan (JTAG) support on all devices 36 to 288 macrocells, with 800 to 6400 usable gates
Features
· Optimized for high-performance 3.3V systems · 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package) Lower power operation 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals 3.3V or 2.5V output capability Advanced 0.35 micron feature size CMOS FastFLASH technology In-system programmable Superior pin-locking and routability with FastCONNECT IITM switch matrix Extra wide 54-input Function Blocks Up to 90 product-terms per macrocell with individual product-term allocation Local clock inversion with three global and one product-term clocks · · · · ·
Four pin-compatible device densities -
Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability 10,000 program/erase cycles endurance rating 20 year data retention
Advanced system features -
Pin-compatible with 5V core XC9500 family in common package footprints
Table 1: XC9500XL Device Family X C 9536X L Macrocells Usable Gates Registers TPD (ns) TSU (ns) TCO (ns) fSYSTEM (MHz) 36 800 36 5 3. 7 3. 5 178 XC9572XL 72 1, 600 72 5 3. 7 3. 5 1 78 XC95144XL 144 3, 200 144 5 3.7 3.5 178 X C 952 88X L 288 6,400 288 6 4.0 3.8 208
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS054 (v1.6) January 24, 2002 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
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XC9500XL High-Performance CPLD Family Table 2: XC9500XL Packages and User I/O Pins (not including 4 dedicated JTAG pins) X C 95 36X L 44-pin PLCC 44-pin VQFP 48-pin 0.8 mm CSP 64-pin VQFP 100-pin TQFP 144-pin 0.8 mm CSP 144-pin TQFP 208-pin PQFP 256-pin BGA 256-pin FBGA 280-pin 0.8 mm CSP 34 34 36 36 XC9572XL 34 34 38 52 72 X C95 144X L 81 117 117 XC95288XL 117 168 192 192 192
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3 JTAG Port
JTAG Controller
In-System Programming Controller
54 I/O I/O I/O FastCONNECT II Switch Matrix I/O 54 18 18
Function Block 1 Macrocells 1 to 18
Function Block 2 Macrocells 1 to 18
I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2 or 4
54 18
Function Block 3 Macrocells 1 to 18
54 18
Function Block N Macrocells 1 to 18
DS054_01_042001
Figure 1: XC9500XL Architecture Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly.
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www.xilinx.com 1-800-255-7778
DS054 (v1.6) January 24, 2002 Preliminary Product Specification
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XC9500XL High-Performance CPLD Family
Family Overview
The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is impor tant. Each XC9500XL device supports in-system programming (ISP) and the full IEEE 1149.1 (JTAG) boundar y-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XL family is designed to work closely with the Xilinx Virtex, Spar tan-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitr y and high-density general purpose logic. As shown in Table 1, logic density of the XC9500XL devices ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500XL family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package footpr int. The XC9500XL architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 5V, 3.3V, and 2.5V inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9500XL device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times.
Architecture Description
Each XC9500XL device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the FastCONNECT II switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with extra wide 54inputs and 18 outputs. The FastCONNECT II switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, up to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs. See Figure 1
Function Block
Each Function Block, as shown in Figure 2 is comprised of 18 independent macrocells, each capable of implementing a combinatorial or registered function. The FB also receives global clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the FastCONNECT switch matrix. These 18 outputs and their corresponding output enable signals also drive the IOB. Logic within the FB is implemented using a sum-of-products representation. Fifty-four inputs provide 108 true and complement signals into the programmable AND-array to form 90 product terms. Any number of these product terms, up to
DS054 (v1.6) January 24, 2002 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
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