|
Details, datasheet, quote on part number:XC95144XV-7TQ100C
| |
Datasheet text preview:
0
R
XC9500XV Family High-Performance CPLD
0 6
DS049 (v2.1) June 24, 2002
Preliminary Product Specification
Features
· Optimized for high-performance 2.5V systems · · 5 ns pin-to-pin logic delays Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package) Lower power operation Multi-voltage operation FastFLASH technology In-system programmable Output banking (XC95144XV, XC95288XV) Superior pin-locking and routability with Fast CONNECTTM II switch matrix Extra wide 54-input Function Blocks Up to 90 product-terms per macrocell with individual product-term allocation Local clock inversion with three global and one product-term clocks Individual output enable per output pin w ith local inversion Input hysteresis on all user and boundary-scan pin inputs Bus-hold circuitry on all user pin inputs Full IEEE Standard 1149.1 boundary-scan (JTAG) support on all devices 36 to 288 macrocells, with 800 to 6400 usable gat es
Family Overview
The XC9500XV family is a 2.5V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. Each XC9500XV device supports in-system programming (ISP) and the full IEEE 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XV family is designed to work closely with the Xilinx SpartanTM-XL and VirtexTM FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. As show n in Table 1, logic density of the XC9500XV devices ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. Multiple package options and associated I/O capacity are show n in Table 2. The XC9500XV family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package footprint. The XC9500XV architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide w orry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. Each user pin is compatible with 3.3V and 2.5V inputs, and the outputs may be configured for 3.3V, 2.5V, or 1.8V operation. The XC9500XV device exhibits symmetric full 2.5V output voltage swing to allow balanced rise and fall times.
Advanced system features
Four pin-compatible device densities -
· · · ·
Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability 20 year data retention ESD protection exceeding 2,000V
Architecture Description
Each XC9500XV device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the Fast C ONNECT II switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability w ith extra wide 54 inputs and 18 outputs. The Fast C ONNECT II switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, up to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs. See Figure 1.
· ·
Pin-compatible with 3.3V core XC9500XL family in common package footprints Hot Plugging capability
© 20 02 Xilinx, Inc. All rig hts reserved. All Xilinx tradema rks, reg istered trademarks, patents, and d isclaimers are a s listed at http:// www. xilinx.com/legal.htm. All oth er tra demarks a nd registered tra demarks are t he property of th eir respect ive owners. All specifica tion s are subject to change with out not ice.
DS049 (v2.1) June 24, 2002 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
1
XC9500XV Family High-Performance CPLD
.
R
3 JTAG Port
JTAG Controller
In-System Programming Controller
54 I/O I/O I/O I/O 18
Function Block 1 Macrocells 1 to 18
Fast CONNECT II Switch Matrix
54 18
Function Block 2 Macrocells 1 to 18
I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 or 4 I/O/GTS
54 18
Function Block 3 Macrocells 1 to 18
54 18
Function Block N Macrocells 1 to 18
DS049_01_041400
Figure 1: XC9500XV Architecture Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly.
Table 1: XC9500XV Device Family X C 95 36X V Macrocells Usable Gates Registers TPD (ns) TSU (ns) TCO (ns) fSYSTEM (MHz) Out put B ank s 36 800 36 5 3.5 3.5 222 1 XC9572XV 72 1, 600 72 5 3. 5 3. 5 2 22 1 X C 951 44X V 144 3,200 144 5 3. 5 3. 5 222 2 XC95288XV 288 6,400 288 6 4 3.8 208 4
2
www.xilinx.com 1-800-255-7778
D S049 (v2.1) June 24, 2002 Preliminary Product Specification
R
XC9500XV Family High-Performance C PLD
Table 2: XC9500XV Packages and User I/O Pins (not including four dedicated JTAG pins) X C 953 6X V 44-pin PLCC 44-pin VQFP 48-pin CSP 100-pin TQFP 144-pin CSP 144-pin TQFP 208-pin PQFP 256-pin FBGA 280-pin CSP 34 34 36 X C9572X V 34 34 38 72 X C9514 4X V 81 117 117 XC95288XV 117 168 192 192
Function Block
Each Function Block, as shown in Figure 2 is comprised of 18 independent macrocells, each capable of implementing a combinatorial or registered function. The FB also receives global clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the Fast CONNECT II switch matrix. These 18 outputs and their corresponding output enable signals also drive the IOB. Logic within the FB is implemented using a sum-of-products representation. Fifty-four inputs provide 108 true and complement signals into the programmable AND-array to form 90 product terms. Any number of these product terms, up to the 90 available, can be allocated to each macrocell by the product term allocator.
Macrocell 1
Programmable AND-Array From Fast CONNECT II Switch Matrix
54
Product Term Allocators
18 18 18
To Fast CONNECT II Switch Matrix OUT To I/O Blocks PTOE
Macrocell 18
1 3
Global Global Set/Reset Clocks
DS049_02_041400
Figure 2: XC9500XV Function Block
DS049 (v2.1) June 24, 2002 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
3
|
|
