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Part: XCR3384XL-10FG324C
Category:
FPGAs/PLDs
-> PLDs (Programmable Logic Devices)
-> CPLDs (Computer PLD)
Description: Coolrunner XPLA3 CPLD Family
Company: Xilinx Corp.
Datasheet: Download XCR3384XL-10FG324C datasheet File size : 496 kB
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Datasheet text preview:
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CoolRunner XPLA3 CPLD
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DS012 (v1.7) June 23, 2003
Preliminary Product Specification · · · · · · · · · · · Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade 5V tolerant I/O pins Input register set up time of 2.5 ns Single pass logic expandable to 48 product terms High-speed pin-to-pin delays of 5.0 ns Slew rate control per output 100% routable Secur ity bit prevents unauthorized access Suppor ts hot-plugging capability Design entry/verification using Xilinx or industry standard CAE tools Innovative Control Term structure provides: - Asynchronous macrocell clocking - Asynchronous macrocell register preset/reset - Clock enable control per macrocell Four output enable controls per function block Foldback NAND for synthesis optimization Universal 3-state which facilitates "bed of nails" testing Available in Chip-scale BGA, Fineline BGA, PLCC, and QFP package
Features
· · · · Fast Zero PowerTM (FZP) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture combines high speed with extreme flexibility Based on industry's first TotalCMOS PLD -- both CMOS design and process technologies Advanced 0.35µ five layer metal EEPROM process - 1,000 erase/program cycles guaranteed - 20 years data retention guaranteed 3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface - Full Boundary Scan Test (IEEE 1149.1) - Fast programming times Ultra-low static power of less than 100 µA Suppor t for complex asynchronous clocking - 16 product term clocks and four local control term clocks per function block - Four global clocks and one universal control term clock per device Excellent pin retention during design changes
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Table 1: CoolRunner XPLA3 Device Family X CR3032X L X CR306 4X L Macrocells 32 64 Usable Gates 750 1, 500 Registers 32 64 TPD (ns) 5 6 TSU (ns) 3. 5 4 TCO (ns) 3. 5 4 213 1 92 Fsystem (MHz)
XCR3128XL 128 3, 000 128 6 4 4 175
X CR3256X L 256 6,000 256 7.5 4.8 4.5 154 X CR32 56X L 120 164 164 164 -
XCR3384XL 38 4 9, 000 38 4 7. 5 4. 8 4. 5 13 5 XCR3384XL 118(1) 172 212 220
X CR35 12X L 512 12,000 512 7. 5 TBD 4. 5 135 X CR3512X L 180 212 260
Table 2: CoolRunner XPLA3 Packages and User I/O Pins X CR3032X L XCR3064XL XCR3128XL 44-pin PLCC 44-pin VQFP 48-pin 0.8mm CSP 56-pin 0.5mm CSP 100-pin VQFP 144-pin 0.8mm CSP 144-pin TQFP 208-pin PQFP 256-pin Fineline BGA 280-pin 0.8mm CSP 324-pin Fineline BGA 36 36 36 36 36 40 48 68 84 10 8 10 8 -
Notes: 1. XCR3384XL TQ144 JTAG pins are not compatible with other members of the XPLA3 family in the TQ144 package.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS012 (v1.7) June 23, 2003 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
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CoolRunner XPLA3 CPLD
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Family Overview
The CoolRunnerTM XPLA3 (eXtended Programmable Logic Array) family of CPLDs is targeted for low power systems that include portable, handheld, and power sensitive applications. Each member of the XPLA3 family includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 100 µA at standby without the need for "turbo bits" or other power dow n schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. CoolRunner devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The CoolRunner XPLA3 family employs a full PLA structure for logic allocation within a function block. The PLA provides maximum flexibility and logic density, with superior pin locking capability, while maintaining deterministic timing. XPLA3 CPLDs are supported by WebPACKTM and WebFITTERTM from Xilinx and industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Viewlogic, andd Synplicity), using text (ABEL, VHDL, Verilog) and schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. The XPLA3 family features also include industry-standard, IEEE 1149.1, JTAG interface through which boundary-scan testing and In-System Programming (ISP) and reprogramming of the device can occur. The XPLA3 CPLD is electrically reprogrammable using industry standard device programmers.
The ZIA is a virtual crosspoint switch. Each function block has 36 inputs from the ZIA and contains 16 macrocells. From this point of view, this architecture looks like many other CPLD architectures. What makes the XPLA3 family unique is logic allocation inside each function block and the design technique used to implement product terms.
Function Block Architecture
Figure 3 illustrates the function block architecture. Each function block contains a PLA array that generates control ter ms, clock terms, and logic cells. A PLA differs from a PAL in that the PLA has a fully programmable AND array followed by a fully programmable OR array. A PAL array has a fixed OR array, limiting flexibility. Refer to Figure 2 for an example of a PAL and a PLA array. The PLA array receives its inputs directly from the ZIA. There are 36 pairs of true and complement inputs from the ZIA that feed the 48 product terms in the array. Within the 48 P-terms there are eight local control terms (LCT[0:7]) available as control signals to each macrocell for use as asynchronous clocks, resets, presets and output enables. If not needed as control terms, these P-Terms can join the other 40 P-Terms as additional logic resources. In each function block there are eight foldback NAND product terms that can be used to synthesize increased logic density in support of wider logic equations. This feature can be disabled in software by the user. As with unused control P-Terms, unused foldback NAND P-Terms can be used as additional logic resources. Sixteen high-speed P-Terms are available at each macrocell for speed critical logic. If wider than a single P-Term logic is required at a macrocell, 47 additional P-Terms can be summed in prior to the VFM (Variable Function Multiplexer). The VFM increases logic optimization by implementing some two input logic funtions before entering the macrocell (see Figure 4). Each macrocell can support combinatorial or registered logic. The macrocell register accommodates asynchronous presets and resets, and "power on" initial state. A hardware clock enable is also provided for either D or T type registers, and the register clock input is used as a latch enable when the macrocell register is configured as a latch function.
XPLA3 Architecture
Figure 1 shows a high-level block diagram of a 128 macrocell device implementing the XPLA3 architecture. The XPLA3 architecture consists of function blocks that are interconnected by a Zero-power Interconnect Array (ZIA).
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DS012 (v1.7) June 23, 2003 Preliminary Product Specification
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CoolRunner XPLA3 CPLD
I/O
MC1 MC2 MC16
FUNCTION BLOCK
36
36
FUNCTION BLOCK
MC1 MC2 MC16
I/O
16
16
16 16
I/O
MC1 MC2 MC16
FUNCTION BLOCK
36
36
FUNCTION BLOCK
MC1 MC2 MC16
I/O
16
16
16
ZIA
16
I/O
MC1 MC2 MC16
FUNCTION BLOCK
36
36
FUNCTION BLOCK
MC1 MC2 MC16
I/O
16
16
16 16
I/O
MC1 MC2 MC16
FUNCTION BLOCK
36
36
FUNCTION BLOCK
MC1 MC2 MC16
I/O
16
16
16 16
DS012_01_112000
Figure 1: Xilinx XPLA3 CPLD Architecture
PLA Array
Inputs
Outputs
PAL Array
Inputs
DS012_08_020601
Figure 2: PLA and PAL Array Example
DS012 (v1.7) June 23, 2003 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
Outputs
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CoolRunner XPLA3 CPLD
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8
Foldback NAND (PT[8:15])
1
To Local Control Term (LCT0)
ZIA
Product Term Array
36 x 48
(PT0)
1
To Local Control Term (LCT7) To Universal Control Term (UCT) Mux
(PT7)
36
(PT[32:47]) P-term Clocks ZIA ZIA
1 (PT16) 48 VFM D Q
I/O1
Macrocell 1 (PT[0:47])
ZIA ZIA
1 48
(PT31)
VFM D Q
I/O16
Macrocell 16 (PT[0:47])
DS012_02_101200
Figure 3: Xilinx XPLA3 Function Block Architecture
From P-term To Combinatorial Path and Register Input From PLA OR Term
DS012_03_121699
Figure 4: Variable Function Multiplexer
Macrocell Architecture
Figure 5 shows the architecture of the macrocell used in the CoolRunner XPLA3. Any macrocell can be reset or preset on power-up. Each macrocell register can be configured as a D-, T-, or Latch-type flip-flop, or bypassed if the macrocell is required as a combinatorial logic function. Each of these flip-flops can be clocked from any one of eight sources or their complements. There are two global synchronous clocks that are selected from the four external clock pins. There is one universal clock signal. The clock input signals CT[4:7] (Local Control Terms) can be individu-
ally configured as either a PRODUCT term or SUM term equation created from the 36 signals available inside the function block. There are two muxed paths to the ZIA. One mux selects from either the output of the VFM or the output of the register. The other mux selects from the output of the register or from the I/O pad of the macrocell. When the I/O pin is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feed back the logic implemented in the macrocell. When an I/O pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the ZIA via the I/O feedback path. The logic
DS012 (v1.7) June 23, 2003 Preliminary Product Specification
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CoolRunner XPLA3 CPLD clock input functions as the latch enable, with the latch transparent when this signal is high. The hard-wired clock enable is non-functional when the macrocell is configured as a latch.
implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. If a macrocell pin is configured as a registered input, there is a direct path to the register to provide a fast input setup time. If the macrocell is configured as a latch, the register
Universal PST CT [0:5] To ZIA
PAD To ZIA From PT Array 1 48 PLA OR Term VFM PST D/T/L Q CT4 P-term CLKEn RST To I/O
Global CLK Global CLK Universal CLK P-term CLK CT [4:7]
Universal RST CT [0:5]
Note: Global CLK signals come from pins.
ds012_05_122299
Figure 5: XPLA3 Macrocell Architecture
I/O Cell
The OE (Output Enable) multiplexer has eight possible modes (Figure 6). When the I/O Cell is configured as an input (or 3-stated output), a half latch feature exists. This half latch pulls the input high (through a weak pullup) if the input should float and cross the threshold. This protects the input from staying in the linear region and causing an increased amount of power consumption. This same weak pull up can be enabled in software such that it is always on when the I/O Cell is configured as an input. This weak pull up is automatically turned on when a pin is unused by the design. The I/O Cell is 5V tolerant when the device is powered. Each output has independent slew rate control (fast or slow) which will assist in reducing EMI emissions. See individual device data sheets for 3.3V PCI electrical specification compatibility. Note that an I/O macrocell used as buried logic that does not have the I/O pin used for input is considered to be unused, and the weak pull-up resistors will be turned on. It is recommended that any unused I/O pins on the XPLA3 family of CPLDs be left unconnected. Dedicated input pins (CLKx/INx) do not have on-chip weak pull-up resistors; therefore unused dedicated input pins must have external ter mination. As with all CMOS devices, do not allow inputs to float.
VCC WP To Macrocell / ZIA From Macrocell Slew Control GND CT Universal OE VCC GND (Weak P.U.)
3 4
Weak Pull-up OE = 7
I/O Pin
OE [2:0]
OE Decode 0 1 2 3 4 5 6 7
I/O Pin State 3-State Function CT0 Function CT1 Function CT2 Function CT6 Universal OE Enable Weak P.U.
ds012_06_121699
Figure 6: I/O Cell
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DS012 (v1.7) June 23, 2003 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
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