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Details, datasheet, quote on part number:XCV100-6PQ240I
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VirtexTM 2.5 V Field Programmable Gate Arrays
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DS003-1 (v2.5 ) April 2, 2001
Product Specification
Features
· Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz - 66-MHz PCI Compliant - Hot-swappable for Compact PCI Multi-standard SelectIOTM interfaces - 16 high-performance interface standards - Connects directly to ZBTRAM devices Built-in clock-management circuitry - Four dedicated delay-locked loops (DLLs) for advanced clock control - Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets Hierarchical memory system - LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register - Configurable synchronous dual-ported 4k-bit RAMs - Fast interfaces to external high-performance RAMs Flexible architecture that balances speed and density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode · Suppor ted by FPGA FoundationTM and Alliance Development Systems - Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager - Wide selection of PC and workstation platforms SRAM-based in-system configuration - Unlimited re-programmability - Four programming modes 0.22 µm 5-layer metal process 100% factory tested
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Description
The Virtex FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 µm CMOS process. These advances make Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex family comprises the nine members shown in Table 1. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
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Table 1: Virtex Field-Programmable Gate Array Family Members Device
XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
System Gates
57,906 108,904 164,674 236,666 322,970 468,252 661,111 888,439 1,124,022
CLB Array
16x24 20x30 24x36 28x42 32x48 40x60 48x72 56x84 64x96
Logic Cells
1,728 2,700 3,888 5,292 6,912 10,800 15,552 21,168 27,648
Maximum Available I/O
180 180 260 284 316 404 512 512 512
Block RAM Bits
32,768 40,960 49,152 57,344 65,536 81,920 98,304 114,688 131,072
Maximum SelectRAM+TM Bits
24,576 38,400 55,296 75,264 98,304 153,600 221,184 301,056 393,216
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-1 (v2.5 ) April 2, 2001 Product Specification
www.xilinx.com 1-800-255-7778
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VirtexTM 2.5 V Field Programmable Gate Arrays
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Virtex Architecture
Vir tex devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing resources. The abundance of routing resources permits the Vir tex family to accommodate even the largest and most complex designs. Vir tex FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. In some modes, the FPGA reads its own configuration data from an external PROM (master serial mode). Otherwise, the configuration data is written into the FPGA (SelectMAPTM, slave serial, and JTAG modes). The standard Xilinx FoundationTM and Alliance SeriesTM Development systems deliver complete design support for Vir tex, covering every aspect from behavioral and schematic entry, through simulation, automatic design translation and implementation, to the creation, downloading, and readback of a configuration bit stream.
Xilinx thoroughly benchmarked the Virtex family. While performance is design-dependent, many designs operated internally at speeds in excess of 100 MHz and can achieve 200 MHz. Table 2 shows performance data for representative circuits, using worst-case timing parameters. Table 2: Performance for Common Circuit Functions Function Register-to-Register Adder Pipelined Multiplier Address Decoder 16:1 Multiplexer Parity Tree 9 18 36 Chip-to-Chip HSTL Class IV LVTTL,16mA, fast slew 200 MHz 180 MHz 16 64 8x8 16 x 16 16 64 5.0 ns 7.2 ns 5.1 ns 6.0 ns 4.4 ns 6.4 ns 5.4 ns 4.1 ns 5.0 ns 6.9 ns Bits Virtex -6
Higher Performance
Vir tex devices provide better performance than previous generations of FPGA. Designs can achieve synchronous system clock rates up to 200 MHz including I/O. Virtex inputs and outputs comply fully with PCI specifications, and interfaces can be implemented that operate at 33 MHz or 66 MHz. Additionally, Virtex supports the hot-swapping requirements of Compact PCI.
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www.xilinx.com 1-800-255-7778
DS003-1 (v2.5 ) April 2, 2001 Product Specification
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VirtexTM 2.5 V Field Programmable Gate Arrays
Virtex Device/Package Combinations and Maximum I/O
Table 3: Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) Package CS144 TQ144 PQ240 HQ24 0 BG256 BG352 BG432 BG560 FG256 FG456 FG676 FG680 176 176 176 260 176 284 312 404 444 512 444 512 512 180 180 180 260 180 260 260 316 316 404 316 404 316 404 404 XCV50 94 98 166 XCV100 94 98 166 166 166 166 166 166 166 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
Virtex Ordering Information
Example:
Device Type Speed Grade -4 -5 -6
XCV300 -6 PQ 240 C
Temperature Range C = Commercial (TJ = 0°C to +85°C) I = Industrial (TJ = 40°C to +100°C) Number of Pins Package Type BG = Ball Grid Array FG = Fine-pitch Ball Grid Array PQ = Plastic Quad Flat Pack HQ = High Heat Dissipation QFP TQ = Thin Quad Flat Pack CS = Chip-scale Package Figure 1: Virtex Ordering Information
DS003-1 (v2.5 ) April 2, 2001 Product Specification
www.xilinx.com 1-800-255-7778
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