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Part: XCV300E-6FG860I
Category:
FPGAs/PLDs
-> FPGA (Field Programmable Gate Array)
Description: Virtex-e Field Programmable Gate Array
Company: Xilinx Corp.
Datasheet: Download XCV300E-6FG860I datasheet File size : 496 kB
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VirtexTM-E 1.8 V Field Programmable Gate Arrays
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DS022-1 (v2.3) July 17, 2002
Production Product Specification
Features
· Fast, High-Density 1.8 V FPGA Family - Densities from 58 k to 4 M system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz Highly Flexible SelectI/O+TM Technology - Suppor ts 20 high-performance interface standards - Up to 804 singled-ended I/Os or 344 differential I/O pairs for an aggregate bandwidth of > 100 Gb/s Differential Signalling Support - LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL - Differential I/O signals can be input, output, or I/O - Compatible with standard differential devices - LVPECL and LVDS clock inputs for 300+ MHz clocks Proprietar y High-Performance SelectLinkTM Technology - Double Data Rate (DDR) to Virtex-E link - Web-based HDL generation methodology Sophisticated SelectRAM+TM Memory Hierarchy - 1 Mb of internal configurable distributed RAM - Up to 832 Kb of synchronous internal block RAM - Tr ue Dual-Port BlockRAM capability - Memor y bandwidth up to 1.66 Tb/s (equivalent bandwidth of over 100 RAMBUS channels) - Designed for high-performance Interfaces to External Memories - 200 MH z ZBT* SRAMs - 200 Mb/s DDR SDRAMs - Suppor ted by free Synthesizable reference design
* ZBT is a trademark of Integrated Device Technology, Inc.
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High-Perfor mance Built-In Clock Management Circuitry - Eight fully digital Delay-Locked Loops (DLLs) - Digitally-Synthesized 50% duty cycle for Double Data Rate (DDR) Applications - Clock Multiply and Divide - Zero-delay conversion of high-speed LVPECL/LVDS clocks to any I/O standard Flexible Architecture Balances Speed and Density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input function - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Inter nal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode Suppor ted by Xilinx FoundationTM and Alliance SeriesTM Development Systems - Fur ther compile time reduction of 50% - Inter net Team Design (ITD) tool ideal for million-plus gate density designs - W ide selection of PC and workstation platforms SRAM-Based In-System Configuration - Unlimited re-programmability Advanced Packaging Options - 0.8 mm Chip-scale - 1.0 mm BGA - 1.27 mm BGA - HQ/PQ 0.18 µm 6-Layer Metal Process 100% Factory Tested
© 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-1 (v2.3) July 17, 2002 Production Product Specification
www.xilinx.com 1-800-255-7778
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VirtexTM-E 1.8 V Field Programmable Gate Arrays
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Table 1: Virtex-E Field-Programmable Gate Array Family Members Device XC V50E X C V 100E X C V 200E X C V 300E X C V 400E X C V 600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E S ystem Gates 71,693 128, 236 306, 393 411, 955 569, 952 985, 882 1,569,178 2,188,742 2,541,952 3,263,755 4,074,387 Logic Gates 20, 736 32, 400 63, 504 82, 944 129,600 186,624 331,776 419,904 518,400 685,584 876,096 CL B Array 16 x 24 20 x 30 28 x 42 32 x 48 40 x 60 48 x 72 64 x 96 72 x 108 80 x 120 92 x 138 104 x 156 Logic Cells 1, 728 2, 700 5, 292 6, 912 10, 800 15, 552 27, 648 34, 992 43, 200 57, 132 73, 008 Differential I/O Pairs 83 83 11 9 13 7 18 3 24 7 28 1 34 4 34 4 34 4 34 4 Use r I/O 176 196 284 316 404 512 660 724 804 804 804 B lockRAM Bits 65,536 81,920 114, 688 131, 072 163, 840 294, 912 393, 216 589, 824 655, 360 753, 664 851, 968 Distributed RAM Bits 24, 576 38, 400 75, 264 98, 304 153,600 221,184 393,216 497,664 614,400 812,544 1,038,336
Virtex-E Compared to Virtex Devices
The Virtex-E family offers up to 43,200 logic cells in devices up to 30% faster than the Virtex family. I/O performance is increased to 622 Mb/s using Source Synchronous data transmission architectures and synchronous system performance up to 240 MHz using singled-ended SelectI/O technology. Additional I/O standards are supported, notably LVPECL, LVDS, and BLVDS, which use two pins per signal. Almost all signal pins can be used for these new standards. Vir tex-E devices have up to 640 Kb of faster (250 MHz) block SelectRAM, but the individual RAMs are the same size and structure as in the Virtex family. They also have eight DLLs instead of the four in Virtex devices. Each individual DLL is slightly improved with easier clock mirroring and 4x frequency multiplication. VCCINT, the supply voltage for the internal logic and memor y, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced processing and 0.18 µm design rules have resulted in smaller dice, faster speed, and lower power consumption. I/O pins are 3 V tolerant, and can be 5 V tolerant with an exter nal 100 resistor. PCI 5 V is not supported. With the addition of appropriate external resistors, any pin can tolerate any voltage desired. Banking rules are different. With Virtex devices, all input buffers are powered by VCCINT. With Virtex-E devices, the LVTTL, LVCMOS2, and PCI input buffers are powered by the I/O supply voltage VCCO.
The Virtex-E family is not bitstream-compatible with the Virtex family, but Virtex designs can be compiled into equivalent Virtex-E devices. The same device in the same package for the Virtex-E and Vir tex families are pin-compatible with some minor exceptions. See the data sheet pinout section for details.
General Description
The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 µm CMOS process. These advances make Virtex-E FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex-E family includes the nine members in Table 1. Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
Virtex-E Architecture
Vir tex-E devices feature a flexible, regular architecture that compr ises an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing
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www.xilinx.com 1-800-255-7778
DS022-1 (v2.3) July 17, 2002 Production Product Specification
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VirtexTM-E 1.8 V Field Programmable Gate Arrays
resources. The abundance of routing resources permits the Vir tex-E family to accommodate even the largest and most complex designs. Vir tex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Configuration data can be read from an external SPROM (master serial mode), or can be written into the FPGA (SelectMAPTM, slave serial, and JTAG modes). The standard Xilinx Foundation SeriesTM and Alliance SeriesTM Development systems deliver complete design suppor t for Virtex-E, covering every aspect from behavioral and schematic entry, through simulation, automatic design translation and implementation, to the creation and downloading of a configuration bit stream.
Table 2: Performance for Common Circuit Functions Function Register-to-Register A dder Pipelined Multiplier Address Decoder 16:1 Multiplexer Par ity Tree 9 18 36 16 64 8x8 16 x 16 16 64 4.3 ns 6.3 ns 4.4 ns 5.1 ns 3.8 ns 5.5 ns 4.6 ns 3.5 ns 4.3 ns 5.9 ns Bits Virtex-E (-7)
Higher Performance
Vir tex-E devices provide better performance than previous generations of FPGAs. Designs can achieve synchronous system clock rates up to 240 MHz including I/O or 622 Mb/s using Source Synchronous data transmission architechtures. Virtex-E I/Os comply fully with 3.3 V PCI specifications, and interfaces can be implemented that operate at 33 MHz or 66 MHz. While performance is design-dependent, many designs operate internally at speeds in excess of 133 MHz and can achieve over 311 MHz. Table 2 shows performance data for representative circuits, using worst-case timing parameters.
Chip-to-Chip HSTL Class IV LVTTL,16mA, fast slew LVD S LVPECL
Virtex-E Device/Package Combinations and Maximum I/O
Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) X CV 50E CS 144 P Q2 4 0 H Q2 4 0 B G3 5 2 B G4 3 2 B G5 6 0 F G2 5 6 F G4 5 6 F G6 7 6 F G6 8 0 F G8 6 0 F G9 0 0 FG1156 512 17 6 176 17 6 28 4 176 312 404 444 512 512 660 660 660 5 12 6 60 7 00 7 24 804 804 80 4 512 660 196 26 0 260 316 316 404 316 404 404 4 04 404 94 15 8 X CV 100E 94 158 X CV 2 00E 94 15 8 158 158 158 158 X CV 300 E X CV 400E X CV 600E XC V 10 00E X CV 1600 E X CV 2000E XCV 26 00E X CV 3200E
DS022-1 (v2.3) July 17, 2002 Production Product Specification
www.xilinx.com 1-800-255-7778
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