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Details, datasheet, quote on part number:XF-TWSI-MS
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| Part: | XF-TWSI-MS |
| Category: | FPGAs/PLDs => FPGA (Field Programmable Gate Array) => FPGA/PLD Soft Core |
| Description: | Xf-twsi-ms Two-wire Serial Interface Master-slave |
| Company: | Xilinx Corp. |
| Datasheet: | Download XF-TWSI-MS datasheet File size : 61 kB |
| Request For quote: | Find where to buy XF-TWSI-MS
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Datasheet text preview:
XF-TWSI-MS Two-Wire Serial Interface Master-Slave
September 16, 1999 Product Specification
AllianceCORETM Facts
Core Specifics See Table 1 Provided with Core Documentation 7810 South Hardy Drive, Suite 104 Tempe, Arizona 85284 USA Phone: +1 888-845-5585 (USA) +1 480-753-5585 Fax: +1 480-753-5899 E-mail: info@memecdesign.com URL: www.memecdesign.com Datasheet, Implementation instructions VHDL Source RTL .ucf VHDL Testbench
Features
· · · · · · I2C-compatible two-wire serial interface core; I2C is a trademark of Philips, Inc. Multi-master operation with arbitration and clock synchronization Slave transmit and receive operation Suppor t for reads, writes, burst reads, burst writes, and repeated start User-defined timing and clock frequency Fast mode and standard mode operation
Design File Formats Constraints File Verification Instantiation VHDL, Verilog Templates Reference designs & None Application notes Additional Items Warranty by MDS Simulation Tool Used Model Technology Support Support provided by Memec Design Services.
Applications
· Embedded microprocessor boards and any circuit needing I2C peripherals.
Table 1: Core Implementation Data CLBs2 Core+ Core Ext logic 156 156 164 164 1852 1852 Clock IOBs 2 2 2 IOBs1 Core+ Core Ext logic 31 29 31 29 31 29
Supported Family 4000XL Spartan Virtex
Device Tested 4005XL-1 S10-4 V50-4
Performance (MHz) 31 30 59
Xilinx Tools M1.5i M1.5i M1.5i
Special Features TBUFs TBUFs TBUFs
Notes: 1. Assuming all core I/O are routed off-chip. 2. Utilization numbers for Virtex are in CLB slices.
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XF-TWSI-MS Two-Wire Serial Interface Master-Slave
External Logic X F T W S I CORE
MPU_DIN[7:0]
I Pad I Pad I Pad I Pad I Pad I Pad I Pad I Pad I Pad I Pad I Pad I Pad I Pad IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF BUFG
External Logic
AT TOP LEVEL
SCL_OUT Shiftlgc SCL_IN
OBUFT
RESET RD_L WR_L W R _ DATA WR_ADDR C M D _ S TAT W R _ OW N _ A D D R WR_FREE_CNT WR_HI_CNT WR_LO_CNT T W S I _ DATA CLK M i c ro P ro c e s s o r Interface C o n t ro l Logic
I/O Pad IBUF OBUFT
S DA _ O U T S DA _ I N
I/O Pad IBUF
S y n ch rs Shift Register
MPU_DOUT[7:0]
(HOST DATA) (STATUS REGISTER)
OBUF O Pad
OBUF O Pad
MPU_DOUT[3:0] State Machine I N T E R RU P T
OBUF
O Pad
>
X8902
Figure 1: XF-TWSI Block Diagram
General Description
XF-TWSI-MS is an industry standard two-wire serial interface supporting multiple masters. This core will operate as a master or a slave. This core does not support General Call Addressing, 10-bit slave addressing, or START byte data transfers. MDS cores are designed with the philosophy that no global elements should be embedded within the core itself. Global elements include any of the following components: STARTUP, STARTBUF, BSCAN, READBACK, Global Buffers, Fast Output Primitives, IOB Elements, Clock Delay Components, and any of the Oscillator Macros. MDS cores only contain resources present in the CLB array. This is done to allow flexibility in using the cores with other logic. For instance, if a global clock buffer is embedded within the core, but some external logic also requires that same clock, then an additional global buffer would have to be used. In any instance, where one of our cores generates a clock, that signal is brought out of the core, run through a global buffer, and then brought back into the core. This philosophy allows external logic to use that clock without using another global buffer. A result of this philosophy is that the cores are not self-contained. External logic must be connected to the core inorder to complete it. MDS cores include tested sample designs that add the external logic required to complete the functionality. This datasheet describes both the core and the supplied external logic. The Absolute Maximum Ratings, Operating Conditions, DC Electrical Specifications, and Capacitance are device
dependent and can be found in the Xilinx datasheet for the target device.
Functional Description
The XF-TWSI-MS is partitioned into modules as shown in Figure 1 and described below.
Microprocessor Interface Control Logic
There are four registers used to interface to the host: the Data Register, the Address Register, the Own_Address Register, and the Command Register. The Own_Address Register is used for slave operations to set the unique address of the device on the IIC bus. The strobes WR_DATA, WR_ADDR, WR_OWN_ADDR, and CMD_STAT are directly connected to the clock enable pins of these register flip-flops for ease of interface.
Shiftlgc
The basic cycle on the XF-TWSI-MS serial interface consists of an address cycle followed by a data cycle. The address consists of seven bits and the read/write bit (the LSB). The MSB is always transmitted first on the SDA line. The data cycle can either be a read or a write. For a write operation the macro shifts the data from the Data Register onto the SDA line. For a read operation the macro captures the data into the Shift Register. The data cycle can end in three different ways: 1. A stop can be generated which terminates the current cycle. 2. Another data cycle can take place (a burst).
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September 16, 1999
Memec Design Services 3. A repeated start can be generated by the inter-face. There is always one interrupt generated for each data cycle independent of the type of cycle. For example, for a burst read cycle an interrupt will be generated for each byte read. For a burst write cycle an interrupt will be generated when each byte transfer is completed. A repeated start is used to turn the bus around; when a read cycle must be followed directly by a write cycle without a stop in-between. Since the READ bit is a part of the address, if a read followed by write is desired without a stop command, a second address must be issued following the data cycle. The sequence of events in a repeated start cycle is: start, address cycle, data cycle, repeated start, address cycle, data cycle, stop. Each of the data cycles can be repeated if bursting is desired, and the stop cycle could actually be another repeated start, if desired.
External Crystal Support
This core does not support connection of a crystal directly to the device; a clock input is required.
Pinout
Due to the open collector nature of the Serial Data (SDA_IN and SDA_OUT) and Serial Clock (SCL_IN and SCL_OUT) pins, the XF-TWSI-MS must be implemented internally with the user's design using an OBUFT and IBUF combination. Signal names are provided in the block diagram shown in Figure 1 and Table 2.
Verification Methods
Complete functional and timing simulation has been performed on the XF-TWSI-MS using Model Technology VSIM. (Simulation command files and test bench used for verification are provided with the core.)
Synchrs
The SDA and SCL inputs are passed through this module that performs a dual-rank synchronization and glitch filtering when enabled by the FILTER_EN signal. The synchronized versions of the SDA and SCL signals are used in all macro modules. The XF-TWSI-MS macro treats both the SDA and SCL lines as data lines. The SDA line is actually sampled some number of clocks after the rising edge of SCL is detected. This allows for greater noise immunity and more robust operation.
Recommended Design Experience
Users should be familiar with VHDL, Xilinx design flows and have experience with microprocessor systems and peripherals. For the source code version, users should also be familiar with Synplicity's synthesis and Model Technology's simulation tools.
Ordering Information
The XF-TWSI Two Wire Serial Interface Core is provided under license from Memec Design Services for use in Xilinx programmable logic devices and Xilinx HardWire gate arrays. Please contact Memec for pricing and more information. Memec Design Services warrants that the design delivered by Memec Design Services will conform to the design specification. This warranty expires 3 months from the date of delivery of the design database. Contact Memec De-sign Ser vices for the Design License Agreement with complete Terms and Conditions of Sale. Information furnished by Memec Design Services is believed to be accurate and reliable. Memec Design Services reserves the right to change specifications detailed in this data sheet at any time without notice, in order to improve reliability, function or design, and assumes no responsibility for any errors within this document. Memec Design Services does not make any commitment to update this information. Memec Design Services assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction, if such be made, nor does the Company assume responsibility for the functioning of undescribed features or parameters. Memec Design Services will not assume any liability for the accuracy or correctness of any support or assistance provided to a user.
State Machine
The control for the serial interface comes from the state machine. This state machine controls the loading and enabling of all shift registers and counters, and is responsible for implementing the basic interface protocol.
Shift Register
There is a single parallel-in, parallel-out, serial-in, serial-out shift register called NUPSHIFT_MS, which performs the shifting of data for address cycles, write cycles, and read cycles. The parallel output drives the macro interface pins MPU_DOUT which are used to return read data to the host.
Core Modifications
With minor exception, the XF-TWSI-MS meets or exceeds the industry standard. However, in most cases the Timespecs can be tightened significantly. Proper operation with 100ns bus cycles has been verified. In all cases, a post-route timing analysis should be performed to verify performance. Implementation beyond specified performance and other customizing is available through Memec Design Services at additional cost.
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