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Details, datasheet, quote on part number:XF8279
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Datasheet text preview:
XF8279 Programmable Keyboard Display Interface
September 16, 1999 Product Specification
AllianceCORE
Device Family CLBs Used Core Core+Ext logic Core I/O Core1 Core+Ext logic System Clock fmax Device Features Used Documentation
TM
Facts
Spartan 183 183 49 38 8 MHz2
Core Specifics XC4000E/XL 183 183 49 38
7810 South Hardy Drive, Suite 104 Tempe, Arizona 85284 USA Phone: +1 888-845-5585 (USA) +1 480-753-5585 Fax: +1 480-753-5899 E-mail: info@memecdesign.com URL: www.memecdesign.com
RAM, OSC4, 3 BUFGs
Features
· · · · · · · · · · · · · Compatible with Xilinx CORE Generator tool Simultaneous keyboard and display operations Scanned keyboard mode Scanned sensor mode Strobed input entry mode 8-character keyboard FIFO 2-key lockout or N-Key rollover with contact debounce Dual 4, 8, or 16 numerical display Single 8 or 16 character display Mode programmable from CPU Right or left entry 16-Byte display RAM Programmable scan timing Interrupt output on key entry
Applications
· User interface for embedded systems
Provided with Core User's guide, application notes, implementation instructions Design File Formats .ngo netlist, Viewlogic source files available extra Constraint Files .ucf Verification Tool Machine-readable simulation vectors for ViewLogic ViewSim, Testbench for VHDL and Verilog Symbols Viewlogic, Foundation, Instantiation templates for VHDL and Verilog Evaluation Model None Reference Designs & Sample designs in Viewlogic, Application Notes Foundation, VHDL, and Verilog Additional Items Warranty by MDS, Netlist only version available on enCORE CD-ROM Design Tool Requirements Xilinx Core Tools Alliance/Foundation 1.4 Support Support provided by Memec Design Services.
Notes: 1. Assuming all core signals are routed off-chip. 2. Minimum guaranteed speed.
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XF8279 Programmable Keyboard Display Interface
External Logic
IBUF I/O Pad
External Logic XF8279 CORE
DB[7:0] O_EN DBO[7:0] DISPLAY
OBUFT
CONTROL/TIMING RD_L_N
IBUF I Pad BUFG I Pad IBUF I Pad IBUF I Pad BUFG
Display Control A[3:0]
O Pad
RD_L WR_L CS_L AO
> > I/O Control
Display RAM
B[3:0]
O Pad
IBUF I Pad
RESET
Control Registers KEYBOARD Debounce & Control
IBUF I Pad IBUF I Pad IBUF I Pad
RL[7:0] SHIFT CNTL
OBUF
BUFG F8M OSC4 Clock Signal Generator IBUF I Pad
GCLK
>
BUFG
CLOCK
Clock Pre scaler
FIFO/RAM
IRQ FIFO/RAM Status & Clear Control Scan Generator BD_L SL[3:0]
O Pad
O Pad O Pad
X8805
Figure 1: XF8279 Programmable Keyboard Display Interface Block Diagram
General Description
The XF8279 is a core logic module specifically designed for Xilinx FPGAs which emulates the functionality of the industry standard 8279 programmable keyboard and display interface. It facilitates upgrading current systems by allowing the designer to incorporate the 8279 function as well as other logic into a single, state of the art FPGA. This core is designed such that it can be instantiated into a Xilinx design and hooked up to I/O buffers and pads, some BUFGs, and the 8 MHz OSC4 module and then compiled to make a device that will plug into an 8279 application. The display portion provides a scanned display interface for LED, incandescent, and other popular display technologies. Both numeric and alphanumeric segment displays may be used as well as simple indicators. The XF8279 has a 16 x 8 display RAM that can be organized into dual 16 x 4 RAMs. The RAM can be loaded or interrogated by the CPU. Both right entry calculator and left entry typewriter display formats are possible. Both read and write of the dis-
play RAM can be done with auto increment of the display RAM address. MDS cores are designed with the philosophy that no global elements should be embedded within the core itself. Global elements include any of the following components: STARTUP, STARTBUF, BSCAN, READBACK, Global Buffers, Fast Output Primitives, IOB Elements, Clock Delay Components, and any of the Oscillator Macros. MDS cores only contain resources present in the CLB array. This is done to allow flexibility in using the cores with other logic. For instance, if a global clock buffer is embedded within the core, but some external logic also requires that same clock, then an additional global buffer would have to be used. In any instance, where one of our cores generates a clock, that signal is brought out of the core, then run through a global buffer, then brought back into the core. This philosophy allows external logic to use that clock without using another global buffer. A result of this philosophy is that the cores are not self-contained. External logic must be connected to the core inor-
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September 16, 1999
Memec Design Services der to complete it. MDS cores include tested sample designs that add the external logic required to complete the functionality. This datasheet describes both the core and the supplied external logic.
Clock Prescalers
The Clock Prescaler divides the external system clock input, CLOCK, by a programmable divisor between 2 and 31 to generate an internal frequency of 100 kHz.
Functional Description
The XF8279 is partitioned into modules as shown in Figure 1 and described below. Refer to the XF8279 Programmable Keyboard Display Interface User's Guide for detailed technical information. The User's Guide is available, directly from MDS.
Scan Generator
The Scan Generator block further divides the output of the Clock Prescaler (nominally 100 kHz) by 64 and resynchronizes it with the internal 8 MHz clock to generate an internal scan clock enable of 1.56 kHz (640µs). This internal scan clock enable increments the scan counter itself which is simply a 4-bit binary counter. The least significant two bits of the counter are decoded to a 1 of 4 scan. A bit in the Mode Set register determines whether the counter outputs (encoded scan) or the decoder outputs (decoded scan) are output from the core on SL[3:0]. When using encoded scan, an external (to the core) 1 of 8 or 1 of 16 decoder is required. Note that both the keyboard matrix and the display use the same scan counter outputs. If the keyboard is in decoded scan, so is the display and therefore it will only display the first four characters in Display RAM. This block also generates the display blanking signal, BD_L. This signal is asserted (low) around each transition of the scan counter to blank the display during digit switching.
Control/Timing Group
The Control/Timing Group is comprised of the I/O Control, Control Registers, Clock Prescaler, and Scan Generator. This group establishes timing and controls the movement of data throughout the XF8279 core.
I/O Control
This block together with the external data bus buffers makes up the microprocessor interface. The 8-bit data output bus, DBO[7:0], provides data from the core during microprocessor read cycles. And the 8-bit input data bus, DB[7:0], provides data to the core during microprocessor write cycles. Typically, the Data Buffers are implemented with OBUFTs and IBUFs external to the core logic. The OBUFTs are enabled with an active low enable, O_EN, which is provided by the core during read cycles. It is simply a logical OR of RD_L and CS_L. Write cycles to the core are performed with WR_L, CS_L, and A0. DB[7:0] and A0 are registered on the rising edge of WR_L only when CS_L is asserted (low). The level of A0 determines whether the core interprets the value on DB[7:0] as a command (A0=1) or as display data (A0=0). The registered signals are resynchronized with the free running 8MHz clock, GCLK, and the appropriate command is executed or display data written. Read cycles from the core are performed with RD_L, CS_L, and A0. The falling edge of RD_L registers the state of A0 when CS_L is asserted (low). If A0 is sampled low, then, depending on the previous command, a value from either the keyboard FIFO/Sensor RAM or the display RAM is presented on the output data bus, DBO[7:0]. If A0 is sampled high, then the status word is presented on DBO[7:0].
Display Group
The Display Group consists of the Display Control block and the Display RAM block. Its function is to provide the display data to a multiplexed display synchronized with the Scan Generator. A mechanism is provided to clear the RAM and to allow the host microprocessor to independently write to either the upper or lower 4-bit nibbles.
Display Control
The Display Control block controls all data flow into and out of the Display RAM. Two counters provide the Display RAM address: the Read/Write address counter and the Display address counter. The Read/Write address counter is loaded when the host microprocessor writes to either the Display RAM Read Address or the Display RAM Write Address command register. A subsequent data read or write (A0=0) by the host microprocessor will be to and from the RAM address held in the counter. If the auto increment feature is enabled, the address will increment automatically after the read or write cycle, thereby, relieving the host microprocessor from writing a display RAM address command for each access. In addition, the write enables to the upper and lower nibbles of the Display RAM can be disabled independently, allowing the host microprocessor to write display data on nibble boundaries. The Display address counter steps through the Display RAM as the scan counter is incremented, providing charac-
Control Registers
Eight control registers can be written by the microprocessor using the command write cycles described above (A0=1). The eight registers are: Mode Set, Prescaler Divisor, FIFO/ RAM Read Address, Display RAM Read Address, Display RAM Write Address, Display Write Mode, Clear, and EOI/ Error Mode. A command write to some of these registers simply loads in a value, e.g. Prescaler Divisor. A command write to some other registers both loads in a value and performs a command, e.g. Display RAM Read Address. September 16, 1999
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