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Details, datasheet, quote on part number:YMU759C-QZ
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Datasheet text preview:
YMU759
MA-2
Outline
PRELIMINARY
May 8 .2000
YMU759 is a synthesis LSI for portable telephone that is capable of playing high quality music by utilizing FM synthesizer and ADPCM decoder that are included in this device. As a synthesis, YMU759 is equipped with Yamaha's original FM synthesizer, with which the device is capable of simultaneously generating up to 16 voices with different tones. Since the device is capable of generating ADPCM data simultaneously synchronous with the play of the FM synthesizer, various sampled voices can be used as sound effects. Since the play data of YMU759 are interpreted at anytime through FIFO, the length of the data (playing period) is not limited, so the device can flexibly support applications such as incoming call melody distribution service. The hardware sequencer built in this device allows playing of complex music without giving excessive load to the CPU of the portable telephones. Moreover, the registers of the FM synthesizer can be operated directly for real time sound generation, allowing, for example, utilization of various sound effects when using the game software installed in the portable telephone.
Features
Equipped with FM sound generator function and ADPCM playback function. Number of voices simultaneously generated When only 2-operator tones are used: up to 16 voices can be generated simultaneously. When only 4-operator tones are used: up to 8 voices can be generated simultaneously. Built-in 4-bits 1ch ADPCM decoder, and supports two kinds of sampling frequency, 4 kHz and 8 kHz. Built-in output 550mW(AVDD=3.6V) speaker amplifier:
Built-in hardware sequencer. Built-in circuit for sound quality correcting equalizer.
Supports stereophonic output. Built-in 16-bit stereophonic D/A converter. Provided with a stereophonic analog output terminal for headphone. 4 wire serial interface or 12 wire parallel interface can be selected. PLL is built-in to support master clock input in 2 MHz to 20 MHz range. Supports power down mode. (Typical current: 1 uA or less)
Power supply is divided into analog power supply for speaker amplifier and power supply for the others. Analog power supply for speaker amplifier (SPVDD): 2.7V~4.5V(Typ 3.6V). Digital power supply for the others(VDD): 2.7V~3.3V(Typ 3.0V)
32-pin plastic QFN.
The contents of this booklet are target specifications and they are subject to change without a prior notice. Please check the finalized specifications before actually using this LSI.
YAMAHA CORPORATION
YMU759 CATALOG CATALOG No.:LSI-4MU759A0 2000.5
YMU759
Terminal configuration
SPOUT2
SPOUT1
EXT2
25
D2
D3
24 23 22
D4
D5
D6
21 20 19 18 17 16 15 14 13 12 11 10
D7
D1 D0 /WR SDIN (/CS) SYNC (A0) SCLK (/RD) SDOUT
26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9
SPVSS SPVDD EQ3 EQ2 EQ1 HPOUT-R HPOUT-L/MONO
CLKI
EXT1
/IRQ
/RST
-2-
IFSEL
PLLC
VDD
VSS
VREF
YMU759
Terminal functions
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name CLKI
EXT1
I/O Ish O O Ish I A A A A A A A A A O I/O I/O I/O I/O I/O I/O I/O
I/O Clock input (2~20MHz) External device control terminal 1 Interruption output Hardware reset input CPU I/F selection
Function
/IRQ /RST IFSEL PLLC VDD VSS VREF HPOUT-L / MONO HPOUT-R EQ1 EQ2 EQ3
SPVDD
L: Serial I/F, H: Parallel I/F
Connection of capacitor for built in PLL Connect 0.01 µF (expected) capacitor between this terminal and VSS. Digital power supply (Typically +3.0V) Connect 0.1 µF and 4.7 µF capacitors between this terminal and VSS Ground Analog reference voltage. Connect 0.1 µF capacitor between this terminal and VSS Headphone L channel output: can be switched to mono through register setting Headphone R channel output Equalizer terminal 1 Equalizer terminal 2 Equalizer terminal 3 Analog power supply (Typically +3.6 V) Connect 0.1 µF and 4.7 µF capacitors between this terminal and SPVSS Analog ground for speaker amplifier Speaker terminal 1 Speaker terminal 2 External device control terminal 2 Parallel I/F data bus 7 Parallel I/F data bus 6 Parallel I/F data bus 5 Parallel I/F data bus 4 (To be open when IFSEL=L) Parallel I/F data bus 3 (To be open when IFSEL=L) Parallel I/F data bus 2 (To be open when IFSEL=L) Parallel I/F data bus 1 (To be open when IFSEL=L) Parallel I/F data bus 0 (To be open when IFSEL=L) Parallel I/F write pulse (To be open when IFSEL=L) IFSEL= L Serial I/F data input IFSEL= H Parallel I/F chip select input IFSEL= L Serial I/F data take-in signal IFSEL= H Parallel I/F address signal IFSEL= L Serial I/F bit clock input IFSEL= H Parallel I/F read pulse Serial I/F data output (Pull up resistance is necessary for the outside)
SPVSS SPOUT1 SPOUT2 EXT2
D7 D6 D5
D4 D3 D2 D1 D0 /WR SDIN (/CS) SYNC (A0) SCLK (/RD) SDOUT
Ish Ish Ish Ish OD
Comment: Ish= Schmitt input, OD= open drain terminal, A= Analog terminal
-3-
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