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Details, datasheet, quote on part number:YSS901-F
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Datasheet text preview:
YSS901
SD
Stereo dipole Preliminary
g Outline
YSS901 is a device that uses the stereo dipole system (SD) with which the transaural system can be constructed. When a stereophonic signal that has been processed with the SD system of this device is inputted to two speakers located adjacently at the center of the field (or to two speakers contained in one cabinet), the virtual sound positioning function of this system produces the stereophonic sound similar to the one that can be obtained by using an ordinary stereophonic sound replay system through the central two speakers. YSS901 has built-in one bit Delta-Sigma type A/D and D/A converters for each of the two channels at its input and output respectively. Thanks to these built-in converters, this device can process analog stereophonic sound signal through the converters in addition to digital stereophonic sound signal. This device performs an advanced convolution through DSP using the FIR filter.
g Features
n Two channel virtual sound positioning by using the stereo dipole system. n Processes analog or digital signals at each of the two channels. n Four types of digital data format are available, including 48 fs Serial-DAC16, 18 and 20 bits, and 64 fs. n Six types of parameter coefficients are built in the device. Additional parameter coefficients can be
downloaded externally. n The parameter control is made through the DC switches or synchronous three-wire serial system. n Uses a clock of 2.822 MHz from the crystal. External clock can also be used. n Has a built-in PLL circuit for generating clock for operation. n Internal operating frequency of 512 fs. n Allows fading in or out the output of the results of the convolution when switching the coefficient. n Power supply voltage: 5 V n Si-gate CMOS process. n 64 QFP
YAMAHA CORPORATION
YSS901CATALOG CATALOG No.: LSI-4SS901A0 1999. 1
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TSTNO TSTNI TST1 XTAL ROUT LOUT DVSS PLLC AVSS TSTCK EXTAL
g Pin configuration
51 N.C DVDD TSTSEL CSEL2 CSEL1 CSEL0 RESETN BSFT1 BSFT0 SCK SI DVSS N.C 1 2 3 4 5 6 64 7 8 9 10 11 12 13 14 15 16 17 18 63 62 61 60 59 58 57 56 55 54 53 52
N.C N.C N.C N.C N.C
50
N.C
49
N.C
48
N.C
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33 32 31 30 29 28 27 N.C AVDD VREF AIL AILOUT AILRET 26 25 24 23 22 21 20 19 AIR AIROUT AIRRET AVSS DVSS TST2 N.C
YSS901
N.C
N.C
N.C
N.C
CSN
DIN
N.C
N.C
N.C
N.C
DVDD
BCLK
DOUT
DVDD
SYNCN
DSEL2
DSEL1
DSEL0
CTLSEL
YSS901
YSS901
g Pin Description
No. Pin name 5 6 7 8 9 10 11 12 13 14 15 21 22 23 24 25 26 27 28 29 30 31 37 38 39 40 41 42 43 44 45 46 47 53 54 55 56 57 58 59 60 61 62 63 DVDD CTLSEL SYNCN BCLK CSN DOUT DIN DSEL2 DSEL1 DSEL0 DVDD TST2 DVSS AVSS AIRRET AIROUT AIR AILRET AILOUT AIL VREF AVDD LOUT ROUT PLLC AVSS EXTAL XTAL DVSS TSTCK TST1 TSTNI TSTNO DVDD TSTSEL CSEL2 CSEL1 CSEL0 RESETN BSFT1 BSFT0 SCK SI DVSS I/O I I I I O I I I I AO AO AI AO AO AI AI AO AO AI I O I O I I I I I I I I Function Digital signal power supply : +5 V Selection of control method Digital input/output synchronization signal Digital input/output bit clock Serial control interface chip select signal Digital signal output Digital signal input Analog/digital input selection Digital input/output format selection Digital input/output format selection Digital signal power supply : +5 V Test (To be open.) Digital signal ground Analog signal ground Right channel analog signal input return Right channel analog signal input out Right channel analog signal input Left channel analog signal input return Left channel analog signal input out Left channel analog signal input Analog signal VREF Analog signal power supply : +5 V Left channel analog signal output Right channel analog signal output PLL auxiliary input Analog signal ground Crystal clock input Crystal clock output Digital signal ground Test (Connect with DVSS.) Test (To be open.) Test (Connect with DVSS.) Test (To be open.) Digital signal power supply: +5 V Test (Connect with DVSS.) Coefficient selection (Enabled when CTLSEL = 0) Coefficient selection (Enabled when CTLSEL = 0) Coefficient selection (Enabled when CTLSEL = 0) Reset signal input Bit shift selection (Enabled when CTLSEL = 0) Bit shift selection (Enabled when CTLSEL = 0) Serial control interface clock input Serial control interface data input Digital signal ground
Notes: 1. Pins of No. 1 to 4, 16 to 20, 32 to 36, 48 to 52 and 64 are to be open. 2. I: input pin O: output pin AI: analog signal input pin AO: analog output pin.
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