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Details, datasheet, quote on part number:YSS902-F
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| Part: | YSS902-F |
| Category: | Multimedia => Audio => Processors |
| Description: | Dolby Digital 5.1chFull Decoder, Dolby Pro-logic Decoder, And Programmable DSP |
| Company: | Yamaha Corporation of America |
| Datasheet: | Download YSS902-F datasheet File size : 639 kB |
| Request For quote: | Find where to buy YSS902-F
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Datasheet text preview:
YSS902
AC3D
Dolby Digital (AC-3) / Pro Logic decoder + Sub DSP
INTRODUCTION
The YSS902 is one chip LSI consisting of two built-in DSP's ; Dolby Digital (AC-3) / Pro Logic (Main DSP) and a sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as virtual surround, by down-loading the program and coefficient.
FEATURERS
Dolby Digital 5.1 channel full decode. 24 bit DSP. (Group-A Dolby Digital decoder) No external memory is required. (Memories for center and surround channel delay are included) Possible to decode multi-language encoded data. (possible to decode based on data-stream-number) AC-3 karaoke mode. Original compression modes as well as four compression modes recommended by Dolby. Dolby Digital decoding latency is fixed to two audio blocks (512 samples). Included de-emphasis filter. Pro Logic decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM. High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original surround, filtering, virtual surround etc. Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz) Reads Dolby Digital decode information through the microprocessor interface. Provide total sixteen I/O ports. Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format. Has a built-in PLL oscillation circuit to generates its own operating clock. Internal operating clock is 25MHz. Supply Voltage: 3.3v for core logic. 5v for I/Os. Power saving mode. Si-gate CMOS process. 100 QFP.(YSS902-F)
Note: "AC-3" and "Pro Logic" are registered trademarks of Dolby Laboratories Licensing Corporation. Use of this LSI must be licensed by Dolby Laboratories Licensing Corporation.
YSS902 CATALOG CATALOG No.:LSI-4SS902A4 1999. 7
YSS902
PIN CONFIGURATION
2
YSS902
PIN FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Name VDD1 RAMCEN RAMA16 RAMA15 SDIB0 SDIB1 SDIB2 XI XO VSS AVDD TEST TEST TEST OVFB TEST TEST TEST CPO AVSS VDD2 SDOA2 SDOA1 SDOA0 RAMA14 RAMA13 RAMA12 RAMA11 RAMA10 VSS VDD1 OPORT0 OPORT1 OPORT2 OPORT3 OPORT4 OPORT5 OPORT6 OPORT7 VSS VDD2 RAMA9 RAMA8 RAMA7 SDOB2 SDOB1 SDOB0 SDBCK1 SDWCK1 VSS VDD2 NONPCM CRC MUTE KARAOKE I /O O O O I+ I+ I+ I O FUNCTION +5V power supply (for I/Os) External SRAM interface /CE External SRAM interface address 16 External SRAM interface address 15 PCM input 0 to Sub DSP PCM input 1 to Sub DSP PCM input 2 to Sub DSP Crystal oscillator connection (6.125MHz - 50.0MHz) Crystal oscillator connection Ground +3.3 V power supply (for PLL circuit) Test terminal (to be open in normal use) Test terminal (to be open in normal use) Test terminal (to be open in normal use) Detection of overflow at Sub DSP Test terminal (to be open in normal use) Test terminal (to be open in normal use) Test terminal (to be open in normal use) Output terminal for PLL, to be connected to ground through the external analog filter circuit Ground (for PLL circuit) +3.3 V power supply (for core logic) PCM output from Main DSP (C, LFE) PCM output from Main DSP (LS, RS ) PCM output from Main DSP (L, R) External SRAM interface address 14 External SRAM interface address 13 External SRAM interface address 12 External SRAM interface address 11 External SRAM interface address 10 Ground +5V power supply (for I/Os) Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Ground +3.3 V power supply (for core logic) External SRAM interface address 9 External SRAM interface address 8 External SRAM interface address 7 PCM output from Sub DSP PCM output from Sub DSP PCM output from Sub DSP Bit clock input for SDOA, SDIB, SDOB Word clock input for SDOA, SDIB, SDOB Ground +3.3 V power supply (for core logic) Detection of non-PCM data Detection of CRC error Detection of auto mute Detection of AC-3 karaoke data 3
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A O O O O O O O O O O O O O O O O O O O O O O I+ I+ O O O O
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