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Details, datasheet, quote on part number:YSS912C-F
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| Part: | YSS912C-F |
| Category: | Multimedia => Audio => Processors |
| Description: | Dolby Digital 5.1ch Full Decoder, Dolby Pro-logic Decoder, DTS Decoder, And Programmable DSP |
| Company: | Yamaha Corporation of America |
| Datasheet: | Download YSS912C-F datasheet File size : 146 kB |
| Request For quote: | Find where to buy YSS912C-F
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Datasheet text preview:
YSS912C
AC3D2
Dolby Digital (AC-3) / Pro Logic / DTS decoder + Sub DSP
INTRODUCTION
The YSS912C is one chip LSI consisting two built-in DSP's ; Dolby Digital (AC-3) / Pro Logic / DTS decoder (Main DSP) and a sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as virtual surround, by down-loading the program and coefficient. Sub DSP is compatible with YSS902, the Sub DSP programs developed for YSS902 are also applicable to YSS912C.
FEATURERS
Pin compatible with YSS902 (AC3D). Dolby Digital (AC-3) / Pro Logic and DTS decode. 24 bit DSP. (Group-A Dolby Digital decoder) No external memory is required (Memory for center and surround channel delay is included) when DTS decoding as well as AC-3 / Pro Logic. Possible to decode multi-language encoded data. (possible to decode based on data-stream-number) AC-3 karaoke mode. Original compression mode as well as four compression modes recommended by Dolby. (when AC-3 decoding) Included de-emphasis filter. Pro Logic decoding for Dolby digital 2 channels decoded signal as well as ordinary PCM. High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original surround , filtering, virtual surround etc. Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz) Reads Dolby Digital (AC-3)/DTS decode information through the microprocessor interface. Provide total sixteen I/O ports. Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format. Has a built-in PLL oscillation circuit to generates its own operating clock. Internal operating clock is 30 MHz. Supply Voltage: 3.3v for core logic. 5v for I/Os. Power saving mode. Si-gate CMOS process. 100 QFP.(YSS912C-F)
Note: "AC-3" and "Pro Logic" are registered trademarks of Dolby Laboratories Licensing Corporation. "DTS" is a registered trademark of DTS, Inc. Use of this LSI must be licensed by both Dolby Laboratories Licensing Corporation and DTS, Inc.
YSS912C CATALOG CATALOG No.:LSI-4SS912C2 1999. 3
YSS912C
PIN CONFIGURATION
VSS IPORT0 IPORT1 IPORT2 IPORT3 IPORT4 IPORT5 IPORT6 IPORT7 VDD2 VSS RAMOEN RAMWEN RAMA0 RAMA1 SDIA1 SDIA0 SDBCK0 SDWCK0 VDD2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
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VDD1 OPORT0 OPORT1 OPORT2 OPORT3 OPORT4 OPORT5 OPORT6 OPORT7 VSS VDD2 RAMA9 RAMA8 RAMA7 SDOB2 SDOB1 SDOB0 SDBCK1 SDWCK1 VSS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VDD1 RAMCEN RAMA16 RAMA15 SDIB0 SDIB1 SDIB2 XI XO VSS AVDD SDIB3 TEST TEST OVFB DTSDATA AC3DATA SDOB3 CPO AVSS VDD2 SDOA2 SDOA1 SDOA0 RAMA14 RAMA13 RAMA12 RAMA11 RAMA10 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS RAMD7 RAMD6 RAMD5 RAMD4 RAMD3 RAMD2 RAMD1 RAMD0 VDD1 RAMA2 SCK SI SO /CS /CSB RAMA3 TEST /IC RAMA4 VSS RAMA5 RAMA6 /SDBCK0 SURENC KARAOKE MUTE CRC NONPCM VDD2
YSS912C
PIN FUNCTION
No. Name I/O O O O I+ I+ I+ I O I+ FUNCTION +5V power supply (for I/Os) External SRAM interface /CE External SRAM interface address 16 External SRAM interface address 15 PCM input 0 to Sub DSP PCM input 1 to Sub DSP PCM input 2 to Sub DSP Crystal oscillator connection (12.288 MHz) Crystal oscillator connection Ground +3.3 V power supply (for PLL circuit) PCM input 3 to Sub DSP Test terminal (to be open in normal use) Test terminal (to be open in normal use) Detection of overflow at Sub DSP Detection of DTS data Detection of AC-3 data PCM output from Sub DSP Output terminal for PLL, to be connected to ground through the external analog filter circuit Ground (for PLL circuit) +3.3 V power supply (for core logic) PCM output from Main DSP (C, LFE) PCM output from Main DSP (LS, RS ) PCM output from Main DSP (L, R) External SRAM interface address 14 External SRAM interface address 13 External SRAM interface address 12 External SRAM interface address 11 External SRAM interface address 10 Ground +5V power supply (for I/Os) Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Ground +3.3 V power supply (for core logic) External SRAM interface address 9 External SRAM interface address 8 External SRAM interface address 7 PCM output from Sub DSP PCM output from Sub DSP PCM output from Sub DSP Bit clock input for SDOA, SDIB, SDOB Word clock input for SDOA, SDIB, SDOB Ground +3.3 V power supply (for core logic) Detection of non-PCM data Detection of AC-3 CRC error Detection of auto mute Detection of AC-3 karaoke data 3 1 VDD1 2 RAMCEN 3 RAMA16 4 RAMA15 5 SDIB0 6 SDIB1 7 SDIB2 8 XI 9 XO 10 VSS 11 AVDD 12 SDIB3 13 TEST 14 TEST 15 OVFB 16 DTSDATA 17 AC3DATA 18 SDOB3 19 CPO 20 AVSS 21 VDD2 22 SDOA2 23 SDOA1 24 SDOA0 25 RAMA14 26 RAMA13 27 RAMA12 28 RAMA11 29 RAMA10 30 VSS 31 VDD1 32 OPORT0 33 OPORT1 34 OPORT2 35 OPORT3 36 OPORT4 37 OPORT5 38 OPORT6 39 OPORT7 40 VSS 41 VDD2 42 RAMA9 43 RAMA8 44 RAMA7 45 SDOB2 46 SDOB1 47 SDOB0 48 SDBCK1 49 SDWCK1 50 VSS 51 VDD2 52 NONPCM 53 CRC 54 MUTE 55 KARAOKE
O O O O A O O O O O O O O O O O O O O O O O O O O O O I+ I+ O O O O
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