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Part: ACE9030MFP1N
Category:
RF & Microwaves
-> Baseband Interfaces
Description: Description = Radio Interface And Twin Synthesizer ;; Package Type = LQFP ;; No. Of Pins = 64
Company: Zarlink Semiconductor
Datasheet: Download ACE9030MFP1N datasheet File size : 484 kB
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Datasheet text preview:
ACE9030
Radio Interface and Twin Synthesiser Preliminary Information
DS4288 ISSUE 2.0 January 1998
ACE9030 is a combined radio interface circuit and twin synthesiser, intended for use in a cellular telephone. The radio interface section contains circuits to monitor and control levels such as transmit power in the telephone, circuits to demodulate the frequency modulated signal to audio, and a crystal oscillator with a frequency multiplier. The Main synthesiser has normal and fractional-N modes both with optional speed-up to select the desired channel. The Auxiliary synthesiser is used for the transmit-receive offset and for modulation. Both sections are controlled by a serial bus and have software selected power saving modes for battery economy. The circuit techniques used have been chosen to minimise external components and at the same time give very high performance.
Ordering Information
Industrial temperature range TQFP 64 lead 10 x 10 mm, 0·5 mm pitch ACE9030M/IW/FP1N - shipped in trays and dry packed ACE9030M/IW/FP1Q - tape & reel and dry packed TQFP 64 lead 7 x 7 mm, 0·4 mm pitch ACE9030M/IW/FP2N - shipped in trays and dry packed ACE9030M/IW/FP2Q - tape & reel and dry packed
DOUT5 DOUT6 DOUT7 FIAB FIA VDDSA VSSSA FIMB FIM VSSD PDI PDP RSMA DECOUP RSC VDDD MODMP MODMIN TEST PDA VDDSUB DOUT3 DOUT4 AMPP2 AMPN2 DAC3 AMPP1 AMPN1 AMP01 ADC2A ADC2B ADC4
Features · Low Power Low Voltage (3·6 to 5·0 V) Operation · Serial Bus Controlled Power Down Modes · Simple Programming Format · Reference Crystal Oscillator · Frequency Multiplier for LO2 Signal · 8·064 MHz Output for External Microcontroller · Main Synthesiser with Fractional-N Option · Auxiliary Synthesiser · Main Synthesiser Speed-up Options · FM Discriminator for 450 kHz or 455 kHz I.F. Signal · Radio System Control Interface · Part of the ACE Integrated Cellular Phone Chipset · TQFP 64 pin 0·4 mm and 0·5 mm pitch packages Related Products ACE9030 is part of the following chipset: · ACE9020 Receiver and Transmitter Interface · ACE9040 Audio Processor · ACE9050 System Controller and Data Modem
ACE9030
DOUT0 VDDX DOUT1 VDDA VSSA LO2 ADC1 ADC3A ADC3B ADC5 DOUT8 DAC2 DAC1 DOUT2 CIN1 CIN2
AMP02 RXCD LATCHC LATCHB DATA CL AFCOUT AUDIO BP AFCIN IREF VSSL VDDL CLK8 C8B VDDSUB2
Note: Pin 1 is identified by moulded spot and by coding orientation
VP64 FP64
Applications · AMPS and TACS Cellular Telephone · Two-way Radio Systems
Figure 1 - Pin connections - top view
POLLING ADC
BUS INTERFACE
LOCK DETECT
TWIN SYNTHESISER
DIGITAL OUTPUTS
+ -
L.F. AMPS CRYSTAL MULTIPLIER CRYSTAL OSCILLATOR 8 MHz PLL TRIMMING DACs AFC MIXER AMP & LIMITER AUDIO DEMOD.
+ -
Figure 2 - ACE9030 Simplified Block Diagram
ACE9030
AMPO1 AMPO2
AMPP1 AMPN1 AMPP2 AMPN2 ADC1
+ - + - ADC1 DOUT0 DOUT1 8 Bit A to D Converter INPUT SCANNER DEMULTIPLEXER DOUT2 REGISTERS SELECTOR SWITCHES VDDL VSSL DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 LEVEL SENSE RXCD VDDX
ADC2A ADC2B ADC3A ADC3B ADC4 ADC5 AFCIN C8B CLK8 LO2
DEFINE LEVELS VREF
VSSA
VDDA
VDDL
VSSL
IREF
DOUT8 AUDIO BP
OSC8 PLL.
DEMOD
+ -
MULT x3, x5
MIXER
AFCOUT
CIN2 CIN1 LATCHB VDDSUB2 VDDSUB DECOUP VDDSA VSSSA FIM FIMB CL DATA LATCHC TEST
CRYSTAL OSC.
XO
DATA & CONTROL FILTER
DAC1 DAC2 DAC3
DAC1 DAC2 DAC3
SERIAL BUS I/O TO RADIO INTERFACE
BAND-GAP REFERENCE
BIAS GEN.
RSC RSMA
MAIN SYNTHESISER with FRACTIONAL-N SERIAL BUS INPUT REGISTERS (SYTHS)
PDP PDI MODMP MODMN
TEST SEL.
REFERENCE DIVIDER
LOCK DETECT
VDDD VSSD
FIA FIAB
AUXILIARY SYNTHESISER
PDA
Figure 3 - ACE9030 Block diagram
2
ACE9030
PIN Descriptions
The relevant supplies (VDD) and grounds (VSS) for each circuit function are listed. All VDD and VSS pins should be used.
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name AMPO2 RXCD LATCHC LATCHB DATA CL AFCOUT AUDIO BP AFCIN IREF VSSL VDDL CLK8 C8B VDDSUB2 CIN2 CIN1 DOUT2 DAC1 DAC2 DOUT8 ADC5 ADC3B ADC3A ADC1 LO2 VSSA VDDA DOUT1 VDDX DOUT0 VDDD RSC DECOUP RSMA PDP PDI VSSD FIM FIMB VSSSA VDDSA FIA FIAB DOUT7 DOUT6 DOUT5 MODMP MODMN TEST PDA VDDSUB DOUT3 DOUT4 AMPP2 AMPN2 DAC3 AMPP1 AMPN1 AMPO1 ADC2A ADC2B ADC4 Description LF amplifier 2 output. Receive carrier detect (ADC1 comparator) output. Synthesiser programme enable input. Radio interface programme enable input. Serial data; programming input, results output. Clock input for programming bus and for I.F. sampling. Output from AFC amplifier after sampling. Output from f.m. discriminator after filtering. Feedback input to audio bandpass filter. Input to AFC amplifier and f.m. discriminator. Bias current input for radio interface, connect setting resistor to ground. Ground for radio interface logic. Power supply to radio interface logic. Output clock at 8·064 MHz, locked to crystal. 8·064 MHz oscillator charge pump output and control voltage input. Second connection for clean positive supply to bias substrate. Connection for crystal oscillator. Connection for crystal oscillator. Digital control output 2. Analog control output 1. Analog control output 2. Digital control output 8. Analog to digital converter input 5. Analog to digital converter input 3B. Analog to digital converter input 3A. Analog to digital converter input 1. Output from crystal frequency multiplier. Ground for radio interface analog parts. Power supply to radio interface analog parts. Digital control output 1. Power supply to DOUT1 and DOUT2 switches. Digital control output 0. Power supply to synthesisers, except input buffers and the bandgap. Fractional-N compensation bias current, resistor to ground. Bandgap reference decoupling capacitor connection. Bias current for synthesiser charge pumps, resistor to ground. Main synthesiser proportional charge pump output. Main synthesiser integral charge pump output. Ground for synthesisers, except input buffers and the bandgap. Main synthesiser positive input from prescaler. Main synthesiser negative input from prescaler. Ground for FIM and FIA input buffers and the bandgap. Power for FIM and FIA input buffers and the bandgap. Auxiliary synthesiser positive input from VCO. Auxiliary synthesiser negative input from VCO. Digital control output 7. Digital control output 6. Digital control output 5. Modulus control output to prescaler - positive sense. Modulus control output to prescaler - negative sense. Test input and output for synthesisers. Auxiliary synthesiser charge pump output. Clean positive supply to bias substrate. Digital control output 3. Digital control output 4. LF amplifier 2 positive input. LF amplifier 2 negative input. Analog control output 3. LF amplifier 1 positive input. LF amplifier 1 negative input. LF amplifier 1 output. Analog to digital converter input 2A. Analog to digital converter input 2B. Analog to digital converter input 4. VDD VDDA VDDL VDDL VDDL VDDL VDDL VDDL VDDA VDDA VDDL VDDL VDDA VDDA VDDL VDDL VDDL VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDX VDDX VDDSA VDDD VDDD VDDSA VDDSA VDDSA VDDSA VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDL VDDL VDDA VDDA VDDL VDDA VDDA VDDA VDDA VDDA VDDA VSS VSSA VSSL VSSL VSSL VSSL VSSL VSSL VSSA VSSA VSSL VSSA VSSL VSSA VSSA VSSL VSSL VSSL VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSSA VSSSA VSSSA VSSD VSSD VSSSA VSSSA VSSSA VSSSA VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSL VSSL VSSA VSSA VSSL VSSA VSSA VSSA VSSA VSSA VSSA
2
ACE9030
Absolute Maximum Ratings
Supply voltage from ground 0·3 V to + 6·0 V (any V DD to any VSS) Supply voltage difference 0·3 V to + 0·3 V (any VDD to any other V DD) Input voltage VSS 0·3 V to VDD + 0·3 V (any input pin to its local VSS and VDD) Output voltage VSS 0·3 V to VDD + 0·3 V (any output pin to its local VSS and VDD) Storage temperature 55 °C to + 150 °C Operating temperature 40 ° C to + 85 ° C These are not the operating conditions, but are the absolute limits which if exceeded even momentarily may cause permanent damage. To ensure sustained correct operation the device should be used within the limits given under Electrical Characteristics. To avoid any possibility of latch-up the substrate connections V DDSUB and VDDSUB2 must be the most positive of all V DD's at all times including during power on and off ramping. As the current taken through these VDD's is significantly less than through the other V DD's this requirement can be easily met by directly connecting all VDD pins to a common point on the circuit board but with the decoupling capacitors distributed to minimise cross-talk caused by common mode currents. If low value series resistors are to be included in the VDD connections, with decoupling capacitors by the ACE9030 pins to further reduce interference, the VDDSUB and V DDSUB2 pins should not have such a resistor in order to guarantee that their voltage is not slowed down at power-on. Power switches to DOUT0 and DOUT1 are supplied from VDDX and are specified for a total current of up to 40 mA so any resistor in the VDDX connection must be very low, around 1, in order to avoid excessive voltage drop; it is recommended that this supply has no series resistor. These two methods are shown in circuit diagrams, figures 4 and 5. In both circuits the main V DD must also have good decoupling.
Main VDD
VDDSUB
VDDSUB2
VDDL
VDDA
VDDX
VDDD
VDDSA
Figure 4 - Typical VDD local decoupling networks without series resistors
Main VDD
No Resistor VDDSUB
No Resistor VDDSUB2 VDDL VDDA
Very Small VDDX VDDD VDDSA
Figure 5 - Typical VDD local decoupling networks with series resistors
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ACE9030
Electrical Characteristics
These characteristics apply over these ranges of conditions (unless otherwise stated): TAMB = 40 °C to + 85 °C, VDD = + 3·6 to + 5·0 V, GND ref. = VSS
D.C. Characteristics
Parameter Power supply Supply current, Radio Interface: Sleep mode Fully operating (excluding IDDX) Supply current, Synthesisers: VDD=5V Main and Auxiliary ON Main ON and Auxiliary in Standby Main in Standby and Auxiliary ON Main and Auxiliary in Standby, with Bandgap off Supply current, Synthesisers: Main and Auxiliary ON Main ON and Auxiliary in Standby Main in Standby and Auxiliary ON Main and Auxiliary in Standby Input and output signals Logic input HIGH (LATCHC, LATCHB, DATA, CL, and TEST) Logic input LOW (LATCHC, LATCHB, DATA, CL, and TEST) Input capacitance (signal pins) Input leakage (signal pins) Logic output HIGH (RXCD, DATA, AFCOUT, TEST and DOUT2, 3 and 4) Logic output LOW (RXCD, DATA, AFCOUT, TEST and DOUT2, 3 and 4) Output ON level, DOUT0 and DOUT1 Output HIGH level, DOUT5, 6 and 7 Output LOW level, DOUT5, 6 and 7 Trimmed output level ON, DOUT8 Level difference, DOUT8 ON ADC reference Output level OFF, DOUT8 MODMP, MODMN output HIGH MODMP, MODMN output LOW Input Schmitt Hysteresis, pins CL, LATCHB, LATCHC, DATA. Analog circuits bias resistor on IREF Min. Typ. Max. Unit Conditions
2.3
2·7 7 5 3.7 3 100
mA mA mA mA mA µA mA mA mA µA
XO, OSC8 on (see Note 1) fREF = 10 MHz fMAIN = 10 MHz fAUX = 10 MHz (see Note 2) fREF = 15 MHz fMAIN = 16 MHz fAUX = 90 MHz (see Note 2)
3 2 2 100
0·7 x VDD 0·3
VDD + 0·3 + 0·8 10 1
V V pF µA V V V V V V mV V V V V k k
Pin voltage VSS to VDD External load: 20 k & 30 pF IOH = 20 mA. IOH = 80 µA IOL = 0.2 µA IOH = 135 to 400 µA.
VDD 0·5 0·4 VDDX 0·2 2·3 3·35 5 VDD/2 + 0·35 VDD/2 1·0 0·3 68 100
2·9 0·3 3·55 + 15 0.4 VDD/2 + 1·0 VDD/2 0·35
IOH = 10 µA IOL = 10 µA
VDD @ 3·75 V VDD @ 4·85 V
Notes 1. The sleep current is specified with the crystal oscillator (XO) and the OSC8 oscillator and PLL running as these are normally needed to provide the clock to the system controller. 2. The terms fREF, fMAIN , and fAUX refer to the frequencies of the Reference inputs (Crystal oscillator, pins CIN1 and CIN2), the Main synthesiser inputs (pins FIM and FIMB) and the Auxiliary synthesiser inputs (pins FIA and FIAB) respectively.
4
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