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Details, datasheet, quote on part number:JUPITER-2NP1S
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Datasheet text preview:
JUPITER
CDMA and FM (AMPS) I/Q Filter Preliminary Information
DS4724 - 3.1 May 1998
The JUPITER circuit is designed for use in dual band and dual mode mobile phones (CDMA/AMPS) and meets the requirements for IS-95 when used with other chips from Mitel that form the Planet chipset. JUPITER is an active filter incorporating circuits for receiving both CDMA and FM (AMPS).
FEATURES s Low Power and Low Voltage Operation with a Sleep Mode s Integrated CDMA and FM Filter with Wide Dynamic Range s Low Inband Gain Ripple Performance and Good I/Q Matching for the Filter ABSOLUTE MAXIMUM RATINGS
20·7V to 15·3V Supply voltage, VCC MAX 230°C to170°C Operating temperature, TOP (at pins) 240°C to 1150°C Storage temperature, TSTG (ambient) 230°C to 1125°C Junction temperature VCC10·6V (Max.) CMOS input logic high, VIH CMOS input logic low, VIL 20·6V (Min.) 20·6V to VCC MAX10·6V Maximum input voltage at all pins
Q_OC_TEST Q_OC_TESTB QIN QINB Q_OFFSET Q_OFFSETB VTEST RTUNE ITUNE QTUNE QBAL QOUT QOUTB VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
JUPITER
I_OC_TEST I_OC_TESTB IIN IINB I_OFFSET I_OFFSETB VEE MODE_CDMA ENABLE ENTEST VREF IOUT IOUTB VEE2
NP28
Fig. 1 Pin connections - top view
ESD PROTECTION
All pins are protected against electrostatic discharge to both supplies. At least 2kV protection is provided to MIL-STD-883D Method 3015.7 (human body model).
ORDERING INFORMATION
JUPITER-1/KG/NP1S
I CHANNEL
IIN IOUT
MODE SELECT INPUTS
MODE CONTROL
FILTER CONTROL GAIN CONTROL VGC
TUNE CONTROLS QBAL
QIN
QOUT
Q CHANNEL
Fig. 2 Simplified block diagram
JUPITER
CIRCUIT DESCRIPTION
The block diagram of the JUPITER filter is shown in Fig. 3. Two tunable active low-pass gyrator filters are designed with balanced I/Q inputs and outputs. CDMA MODE In CDMA mode the filter (F1 on Fig. 3) is a 7th order 0.1dB ripple continuously tunable elliptic type with the corner frequency tuned to 690kHz for best stop band attenuation and minimal phase error (in the overall system). Variable gain stages after the filter provide the gain control capability. Overall, each of the CDMA I/Q channels has 45dB nominal voltage gain with the Q channel having ±2dB gain adjustment range. Separate I/Q frequency tuning functions are built into the device. FM MODE In FM mode the same filter is used; however, the biasing is designed such that the current density in the transconductor cells is reduced by a factor of 46, changing the filter's cutoff frequency to 15kHz. The filter characteristic of the main channel filter (gyrator filter) remains the same, i.e. a 0.1dB 7th order elliptic. In FM mode additional 2nd order Sallen and Key 0.1dB ripple Chebeyshev filters (F2) are included in the signal path prior to the gyrators. These improve the out-of-band blocking of the overall filter. Different amplifiers are used in FM mode to those used in CDMA mode to enable optimization of the gain distribution in FM mode for current consumption and dynamic range. OPERATION Signal inputs are DC coupled in both CDMA and FM modes. The device modes are selected by CMOS compatible logic signals as shown in Table 2. An external resistor should be connected between RTUNE and ground to set internal currents; a resistor with a tolerance of 65% and a temperature coefficient of less than 100ppm is recommended. VREF (pin 18) should be decoupled to VCC to give optimum supply rejection. A test mode is provided for filter calibration. In this mode, a test signal is applied to the VTEST input (pin 7) with ENTEST held high. The test mode is designed to interface with the PLUTO baseband processor, which can provide the test signal and I/QTUNE voltages and calibrates the filters using an internal auto calibration algorithm. The algorithm generates two test frequencies and calibrates the filters to give the correct attenuation at the upper frequency. The calibration is normally carried out in CDMA mode: the FM filter performance is scaled accordingly. Pins are provided for DC offset control for I and Q channels (I_OFFSET, I_OFFSETB, Q_OFFSET and Q_OFFSETB). In typical operation, the I_OFFSET/Q_OFFSET pins would be controlled by a voltage derived from the baseband processor. However, it is also possible to minimise the DC offset using external components; this is primarily intended for test purposes. These feedback components between IOUT/QOUT and I_OFFSET/Q_OFFSET are shown in Fig. 4 but would not be used in the normal application In test mode, these offset controls are disabled and the offsets are controlled using on-chip feedback. The loop filter for this feedback uses external 10nF capacitors on pins I_OC_TEST/B and Q_OC_TEST/B as shown in Fig. 4.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Name Q_OC_TEST Q_OC_TESTB QIN QINB Q_OFFSET Q_OFFSETB VTEST RTUNE ITUNE QTUNE QBAL QOUT QOUTB VCC VEE2 IOUTB IOUT VREF ENTEST ENABLE MODE_CDMA VEE I_OFFSETB I_OFFSET IINB IIN I_OC_TESTB I_OC_TEST
I/O I I I I I I I I I I O O P P O O I I I P I I I I I I
Description Q channel offset control in test mode Q channel offset control in test mode (balanced) Q channel CDMA/FM input. Q channel CDMA/FM input (balanced) Q channel offset control Q channel offset control (high gain mode) Test mode signal input for tuning operation Precision resistor for current definition (18k) I filter tuning control Q filter tuning control Q channel gain adjust voltage, VGC Q channel CDMA/FM output Q channel CDMA/FM output (balanced) Supply Ground I channel CDMA (balanced) I channel CDMA Reference voltage decouple Mode control (see Table 2) Mode control (see Table 2) Mode control (see Table 2) Ground (substrate) I channel offset control (high gain mode) I channel offset control I channel CDMA (balanced) I channel CDMA I channel offset control in test mode (balanced) I channel offset control in test mode
Table 1 Pin descriptions
2
JUPITER
Q_OC_TEST
1
Q_OC_TESTB
2
Q_OFFSET Q_OFFSETB
5 6
50k
gm gm
Q CHANNEL ± 2dB
F2 -0·1 dB gm F3
VGC
11
QBAL
QIN QINB
3 4
12
ATTENUATOR
gm F1
X1
13
QOUT QOUTB
ENTEST ENABLE MODE_CDMA VTEST
19 20 21 7
10
MODE CONTROL
gm
FILTER CONTROL
8 9
QTUNE RTUNE ITUNE
IIN IINB
26 25
F1
17
ATTENUATOR
gm
X1
16
IOUT IOUTB
15
-0·1 dB F2
gm F3
22 14 18
VEE2 VEE VCC VREF
I_OFFSET I_OFFSETB
24 23
50k
gm gm
28 27
I_OC_TEST
I_OC_TESTB
Fig. 3 Block diagram
Description Sleep mode CDMA mode FM mode CDMA filter testmode FM filter test mode Disallowed mode ENABLE 0 1 1 1 1 0 MODE_ ENTEST CDMA X 1 0 1 0 X 1 0 0 1 1 0 Comments All circuits powered down Biasing and CDMA signal path on Biasing and FM signal path on Biasing, CDMA test and CDMA signal path on, excluding input amplifier Biasing, FM test and FM signal path on, excluding input amplifier. This is functionally the same as sleep mode but has higher ICC. In sleep mode PLUTO applies a logic high to ENTEST
Table 2 Truth table for mode control lines
3
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