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Details, datasheet, quote on part number:MT8806APR
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| Part: | MT8806APR |
| Category: | Analog & Mixed-Signal Processing => Switches & Multiplexers => Analog Switches => Low (RDSon) Cross Point Switches |
| Description: | Description = 8 X 4 Analog Switch Array With Low On-resistance, For (VDD - VEE) =4. 5V to 13.2V ;; Package Type = PLCC ;; No. Of Pins = 28 |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT8806APR datasheet File size : 497 kB |
| Request For quote: | Find where to buy MT8806APR
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Datasheet text preview:
ISO-CMOS MT8806 8 x 4 Analog Switch Array
Features
· · · · · · · · · · Inter nal control latches and address decoder Shor t set-up and hold times Wide operating voltage: 4.5V to 13.2V 12Vpp analog signal capability RON 65 max. @ VDD=12V, 25°C RON 10 @ VDD=12V, 25°C Full CMOS switch for low distortion Minimum feedthrough and crosstalk Separate analog and digital reference supplies Low power consumption ISO-CMOS technology
ISSUE3
March 1997
Ordering Information MT8806AE 24 Pin Plastic DIP MT8806AP 28 Pin PLCC -40° to 85°C
Description
The Zarlink MT8806 is fabricated in Zarlink's ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x 4 array of crosspoint switches along with a 5 to 32 line decoder and latch circuits. Any one of the 32 switches can be addressed by selecting the appropriate five address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. VSS is the ground reference of the digital inputs. The range of the analog signal is from VDD to VEE. Chip Select (CS) allows the crosspoint array to be cascaded for matrix expansion.
Applications
· · · · · · Key systems PBX systems Mobile radio Test equipment/instrumentation Analog/d i g i t a l multiplexers Audio/Vid e o switching
CS
STROBE
DATA RESET
VDD
VEE
VSS
1 AX0
1 ················
AX1 AY0 AY1 AY2 32 32
5 to 32 Decoder
Latches
8x4 Switch Array
Xi I/O (i=0-3)
···················
Yi I/O (i=0-7)
Fi g u r e 1 - Functional Block Diagram
3-9
MT8806
ISO-CMOS
24 PIN PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin # Name
PDIP PLCC
Description Y2-Y0 Analog (Inputs/Outputs): these are connected to the Y2-Y0 columns of the switch array. DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. X0 Analog (Input/Output): this is connected to the X0 row of the switch array. X0 Address Line (Input). X1 Analog (Input/Output): this is connected to the X1 row of the switch array. X1 Address Line (Input). X2 Analog (Input/Output): this is connected to the X2 row of the switch array. Chip Select (Input): this is used to select the device. Active High. X3 Analog (Input/Output): this is connected to the X3 row of the switch array. Digital Ground Reference. Negative Power Supply.
1-3 4 5 6 7 8 9 10 11 12 13 14-16 17
1-3 6 7 8 9 10 11 12 13 14 15
Y2-Y0 DATA X0 AX0 X1 AX1 X2 CS X3 VSS VEE
16,17, AY0-AY2 Y0 -Y2 Address Lines (Inputs). 20 21 STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. RESET Y7-Y3 VDD NC Master RESET (Input): this is used to turn off all switches regardless of the condition of CS. Active High. Y7-Y3 Analog (Inputs/Outputs): these are connected to the Y7-Y3 columns of the switch array. Positive Power Supply. No Connect.
18 19-23 24
22 23-27 28 4, 5, 18, 19
3-10
CS X3 VSS VEE AY0 AY1 NC
Y2 Y1 Y0 DATA X0 AX0 X1 AX1 X2 CS X3 VSS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD Y3 Y4 Y5 Y6 Y7 RESET STROBE AY2 AY1 AY0 VEE
4 3 2 1 28 27 26
·
NC Y0 Y1 Y2 VDD Y3 Y4
12 13 14 15 16 17 18
NC DATA X0 AX0 X1 AX1 X2
5 6 7 8 9 10 11
25 24 23 22 21 20 19
Y5 Y6 Y7 RESET STROBE AY2 NC
28 PIN PLCC
ISO-CMOS
Functional Description
The MT8806 is an analog switch matrix with an array size of 8 x 4. The switch array is arranged such that there are 8 columns by 4 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when tur ned on and provide a high degree of isolation when turned off. The control memory consists of a 32 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0 & AX1). Data is presented to the memory on the DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and the STROBE inputs are high and is latched on the falling edge of STROBE. A logical "1" written into a memory cell turns the corresponding crosspoint switch on and a logical "0" turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memor y. The remaining switches retain their previous states. Any combination of X and Y inputs/ outputs can be interconnected by establishing appropriate patterns in the control memory. A logical "1" on the RESET input will asynchronously return all memor y locations to logical "0" turning off all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins (VSS and VEE) are provided for the MT8806 to enable switching of negative analog signals. The range for digital signals is from VDD to VSS while the range for analog signals is from VDD to VEE. VSS and VEE pins can be tied together if a single voltage reference is needed.
MT8806
Address Decode
The five address inputs along with the STROBE and CS (Chip Select) inputs are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low and CS must go high while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch.
3-11
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