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Details, datasheet, quote on part number:MT8812
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| Part: | MT8812 |
| Category: | Analog & Mixed-Signal Processing => Switches & Multiplexers => Analog Switches |
| Description: | 8 X 12 Analog Switch Array With Low On-resistance, For VDD = 4.5V to 14.5V |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT8812 datasheet File size : 538 kB |
| Request For quote: | Find where to buy MT8812
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Datasheet text preview:
ISO-CMOS MT8812 8 x 12 Analog Switch Array
Features
· · · · · · · · · Inter nal control latches and address decoder Shor t set-up and hold times Wide operating voltage: 4.5V to 14.5V 14Vpp analog signal capability RON 65 max. @ VDD=14V, 25°C RON 10 @ VDD=14V, 25°C Full CMOS switch for low distortion Minimum feedthrough and crosstalk Low power consumption ISO-CMOS technology
ISSUE 6
March 1997
Ordering Information MT8812AE MT8812AP 40 Pin Plastic DIP 44 Pin PLCC 0° to 70°C
Description
The Zarlink MT8812 is fabricated in Zarlink's ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven input bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input.
Applications
· · · · · PBX systems Mobile radio Test equipment /instrumentation Analog/d i g i t a l multiplexers Audio/Vid e o switching
STROBE
DATA RESET
VDD
VSS
1 AX0 AX1 AX2 AX3 AY0 AY1 AY2 96
1 ················
7 to 96 Decoder
Latches
8 x 12 Switch Array
96
Xi I/O (i=0-11)
···················
Yi I/O (i=0-7)
Fi g u r e 1 - Functional Block Diagram
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MT8812
ISO-CMOS
NC AX0 AX3 RESET AY2 Y3 VDD Y2 DATA Y1 Y0 NC NC X6 X7 X8 X9 X10 X11 NC NC NC 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 Y7 Y6 STROBE Y5 VSS Y4 AX1 AX2 AY0 AY1 NC 44 PIN PLCC NC NC X0 X1 X2 X3 X4 X5 NC NC NC
Y3 AY2 RESET AX3 AX0 NC NC X6 X7 X8 X9 X10 X11 NC Y7 NC Y6 STROBE Y5 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD Y2 DATA Y1 NC Y0 NC X0 X1 X2 X3 X4 X5 NC NC AY1 AY0 AX2 AX1 Y4
40 PIN PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 3 4,5 6,7 8-13 14 15 16 17 18 1 2 3 4,5 6-8 9-14 Name Y3 AY2 RESET AX3,AX0 NC X6-X11 Description
19 20 21 22, 23 24, 25 26, 27 28 - 33 34 35 36 37 38 39 40
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Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. Y2 Address Line (Input). Master RESET (Input): this is used to turn off all switches. Active High. X3 and X0 Address Lines (Inputs). No Connection. X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. 15-17 NC No Connection. 18 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. NC No Connection. 19 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. 20 STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. 21 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. 22 VSS Ground Reference. 23 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. 24,25 AX1,AX2 X1 and X2 Address Lines (Inputs). 26,27 AY0,AY1 Y0 and Y1 Address Lines (Inputs). 28-31 NC No Connection. 32-37 X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. 38,39 NC No Connection. 40 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. NC No Connection. 41 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. 42 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 43 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. Positive Power Supply. 44 VDD
ISO-CMOS
Functional Description
The MT8812 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there are 8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X input/output lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are selected by the address input lines (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input line. Data is asynchro-nously written into memor y whenever the STROBE input is high and is latched on the falling edge of STROBE. A logical "1" written into a memory cell turns the corresponding crosspoint switch on and a logical "0" turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y lines can be interconnected by establishing appropriate patterns in the control memor y. A logical "1" on the RESET input line will asynchronously return all memory locations to logical "0" turning off all crosspoint switches.
MT8812
Address Decode
The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of STROBE in order for correct data to be written to the latch.
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