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Details, datasheet, quote on part number:MT88L70AS
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| Part: | MT88L70AS |
| Category: | Communication => Telephony => DTMF (Dual Tone Multiple Frequency) => DTMF Receivers |
| Description: | Description = 3 Volt Integrated DTMF Receiver ;; Package Type = SOIC(W) ;; No. Of Pins = 18 |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT88L70AS datasheet File size : 530 kB |
| Request For quote: | Find where to buy MT88L70AS
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Datasheet text preview:
ISO2-CMOS MT88L70 3 Volt Integrated DTMF Receiver
Features
· · · · · · · · · 2.7 - 3.6 volt operation Complete DTMF receiver Low power consumption Inter nal gain setting amplifier Adjustabl e guard time Central office quality Power-dow n mode Inhibit mode Function a l l y compatible with Zarlink's MT8870D
ISSUE 4 March 1997
Ordering Information MT88L70AE 1 8 Pin Plastic DIP MT88L70AS 1 8 Pin SOIC MT88L70AN 2 0 Pin SSOP -40 °C to + 85 °C
Description
The MT88L70 is a complete 3 Volt, DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus interface.
Applications
· · · · · · Paging systems Repeate r systems/mobile radio Credit card systems Remote control Personal computers Telephon e answering machine
VDD
VSS
VRef
INH
PWDN
Bias Circuit
VRef Buffer Q1
Chip Chip Power Bias IN + IN GS Dial Tone Filter
High Group Filter Zero Crossing Detectors Low Group Filter
Digital Detection Algorithm
Code Converter and Latch
Q2
Q3 Q4
to all Chip Clocks
St GT
Steering Logic
OSC1
OSC2
St/GT
ESt
STD
TOE
Fi g u r e 1 - Functional Block Diagram
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MT88L70
IN+ INGS VRef INH PWDN OSC1 OSC2 VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE IN+ INGS VRef INH PWDN NC OSC1 OSC2 VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD St/GT ESt StD NC Q4 Q3 Q2 Q1 TOE
18 PIN PDIP/SOIC
20 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin # Name 18 1 2 3 4 5 6 7 8 9 10 20 1 2 3 4 5 6 8 9 10 11 IN+ INGS VRef INH Non-Inverting Op-Amp (Input). Inverting Op-Amp (Input). Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Figure 5 and Figure 6). Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. Description
PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This pin input is internally pulled down. OSC1 OSC2 VSS TOE Clock (Input). Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit. Ground (Input). 0V typical. Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled up internally.
11- 1214 15 15 17
Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance. StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt. Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply (Input). +3V typical. No Connection.
16
18
ESt
17
19
St/GT
18
20 7, 16
VDD NC
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MT88L70
Functional Description
Digit TOE L H H H H H H H H H H H H H H H H H H H H INH X X X X X X X X X X X X X L L L L H H H H ESt H H H H H H H H H H H H H H H H H L L L L undetected, the output code will remain the same as the previous detected code Q4 Z 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Q3 Z 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Q2 Z 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Q1 Z 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
The MT88L70 monolithic DTMF receiver offers small size, low power consumption and high performance, with 3 volt operation. Its architecture consists of a bandsplit filter section, which separates the high and low group tones, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. Filter Section Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies. The filter section also incor porates notches at 350 and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals. Decoder Section Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the "signal condition" in some industry specifications) the "Early Steering" (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state (see "Steering Circuit"). Steering Circuit Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is perfor med by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 3) to rise as the capacitor discharges. Provided signal condition is maintained (ESt remains high) for the
ANY 1 2 3 4 5 6 7 8 9 0 * # A B C D A B C D
Table 1. Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE X = DON`T CARE
validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a shor t delay to allow the output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor perfor mance to meet a wide variety of system requirements. Guard Time Adjustment In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown in Figure 3 is applicable. Component values are chosen according to the formula:
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