|
Details, datasheet, quote on part number:MT88L89AE
| |
| Part: | MT88L89AE |
| Category: | Communication => Telephony => DTMF (Dual Tone Multiple Frequency) => DTMF Transceivers |
| Description: | Description = 3V Integrated DTMF Transceiver With Adaptive Micro Interface ;; Package Type = Pdip ;; No. Of Pins = 20 |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT88L89AE datasheet File size : 760 kB |
| Request For quote: | Find where to buy MT88L89AE
|
| |
Datasheet text preview:
MT88L89
3V Integrated DTMF Transceiver with Adaptive Micro Interface
Features
· · · · · · · · Complete DTMF transmitter/receiver Low voltage operation (2.7-3.6V) Pin for pin compatible with existing MT8880, MT8888 and MT8889 devices Adaptive micro interface enables compatibility with Intel and Motorola processors DTMF transmitter/receiver power-down via register control Adjustabl e guard time Automatic tone burst mode Call progress tone detection to -30dBm
DS5033 ISSUE 3 January 1999
Ordering Information MT88L89AE 20 Pin Plastic DIP MT88L89AS 2 0 Pin SOIC MT88L89AN 2 4 Pin SSOP MT88L89AP 28 Pin PLCC -40°C to +85°C
Description
The MT88L89 is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability. The receiver section is based upon the industry standard MT8870 DTMF receiver. The transmitter utilizes a switched capacitor D/A converter for low distor tion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. The MT88L89 utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. The MT88L89 provides enhanced power-down features. The transmitter and receiver may independently be powered down via register control.
Applications
· · · · · · Credit card systems Paging systems Repeate r systems/mobile radio Interconn e c t dialers Pay phones Remote monitor/Control systems
TONE
D/A Converters
Row and Column Counters
Transmit Data Register Status Register
Data Bus Buffer
D0 D1 D2 D3
Tone Burst Gating Cct. IN+ INGS OSC1 OSC2 Oscillator Circuit Bias Circuit VDD VRef VSS + Dial Tone Filter
Control Logic
Interrupt Logic IRQ/CP
High Group Filter Low Group Filter Control Logic
Digital Algorithm and Code Converter
Control Register A Control Register B I/O Control
DS/RD CS R/W/WR RS0
Steering Logic
Receive Data Register
ESt
St/GT
Fi g u r e 1 - Functional Block Diagram
4-123
MT88L89
IN+ INGS VRef VSS OSC1 OSC2 TONE R/W/WR CS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD St/GT ESt D3 D2 D1 D0 IRQ/CP DS/RD RS0 IN+ INGS VRef VSS OSC1 OSC2 NC NC TONE R/W/WR CS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD St/GT ESt D3 D2 D1 D0 NC NC IRQ/CP DS/RD RS0
GS NC ININ+ VDD St/GT EST
4 3 2 1 28 27 26
·
20 PIN /PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin # 20 1 2 3 4 5 6 7 24 1 2 3 4 5 6 7 28 1 2 4 6 7 8 9 Name IN+ INGS VRef VSS OSC1 OSC2 Non-inverting op-amp input. Inverting op-amp input. Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference Voltage output (VDD/2). Ground (0V). Oscillator input. This pin can also be driven directly by an external clock. CMOS compatible. Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally. Output from internal DTMF transmitter. High impedance when TOUT bit in Control Register A (CRA) is set to low. Requires resistive termination to VSS. (Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible. Chip Select input must be gated externally by either address strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal, depending on processor used. See Figure 12. Must not be tied low. CMOS compatible. Register Select input. Refer to Table 3 for bit interpretation. CMOS compatible. Description
8 9 10
10 11 12
12 13 14
TONE R/W (WR) CS
11 12 13
13 14 15
15
RS0
17 DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only required when the device is being accessed. CMOS compatible. 18 IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 10. D0-D3 ESt Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1 (Intel). CMOS compatible. Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
14- 18- 1917 21 22 18 22 26
4-124
TONE R/W/WR CS RS0 NC DS/RD IRQ/CP
12 13 14 15 16 17 18
NC VRef VSS OSC1 OSC2 NC NC
5 6 7 8 9 10 11
25 24 23 22 21 20 19
NC NC NC D3 D2 D1 D0
28 PIN PLCC
MT88L89
Pin Description
Pin # 20 19 24 23 28 27 Name St/GT Description Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply (3V typ.).
20
24
28
VDD
Functional Description
The MT88L89 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an inter nal gain setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected. The adaptive micro interface allows various microcontrollers to access the MT88L89 internal registers. Power-Down The MT88L89 provides enhanced power-down functionality to facilitate minimization of supply current consumption. DTMF transmitter and receiver circuit blocks can be independently powered down via register control. When asserted, RxEN control bit powers down all analog and digital circuitry associated solely with the DTMF and Call Progress receiver. The TOUT control bit is used to disable the transmitter and put all circuitry associated only with the DTMF transmitter in power-down mode. With the TOUT control bit is set to zero, the TONE output pin is held in a high impedance (floating) state. When both transmitter and receiver circuits are powered down, circuits utilized by both the DTMF transmitter and receiver are also powered down. This powerdown control disables the crystal oscillator, and the VRef generator. In addition, the IRQ, TONE output and DATA pins are held in a high impedance state. Input Configuration The input arrangement of the MT88L89 provides a differential-input operational amplifier as well as a bias source (VRef), which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-amp output (GS) for gain adjustment.
For applications which are required to meet a guaranteed RX input level of -29dBm over the full temperature and supply voltage range, a unity gain input configuration as shown in Figures 3 and 4 can be used. For applications which require signal detection lower than -29dBm, the external resistors can be configured to give adequate gain. For example, if the application requires tone detection of -31dBm, the input gain can be set to +2dB with the external resistors (see Figures 13 and 14 for value of resistors). However, when +2dB gain is used, the corresponding maximum input signal level must not exceed -6dBm. Receiver Section Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies (see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.
4-125
|
|
