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Details, datasheet, quote on part number:MT88V32
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| Part: | MT88V32 |
| Category: | Multimedia => Video => Switches |
| Description: | 8 X 4 High Performance Video Switch Array (200 MHZ Bandwidth), For (VDD - VEE) = 4.5 V to 13.2 V |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT88V32 datasheet File size : 534 kB |
| Request For quote: | Find where to buy MT88V32
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Datasheet text preview:
MT88V32
8 x 4 High Performance Video Switch Array Preliminary Information
Features
· · · · · · · · · · · 32 bidirectional CMOS "T" switches in an 8×4 non-blocking array Break-be fo re -ma ke switching configuration Fast setup & hold times for switch programming 3dB bandwidth of 200MHz Low feedthrough and crosstalk, better than -80dB at 5MHz Ver y low differential gain and phase errors 12Vpp bipolar signal capability On-state resistance 75 (max) for VDD=+5V, V EE=-7V Switch control through 2-stage latches Or thogon a l Xi and Yi pin connections for optimized PCB layout Latch readback capability for monitoring
ISSUE 1 August 1993
Ordering Information MT88V32AP 44 Pin PLCC -40° to 85°C
Description
The MT88V32 is a digitally programmable (TTL levels) 8×4 crosspoint switch that is designed to control wide-band analog (video) signal. Each of the 32 nodes of the switching matrix has a Tswitch, see Fig.1. This grounds the nodes of all open connections, which greatly reduces feedthrough noise. In order to reduce crosstalk, individual analog signal lines are isolated by interleaving them with ground lines. The two stage programmable latch system allows the state of all switching nodes to be updated simultaneously. The next state of the switch is written into the first stage of the latches through individual write cycles. These changes will not affect the current state of the switch. The STROBE2 control input is used to load the state of all first stage latches to the second stage latches, which updates the complete matrix. Therefore, all 32 switching nodes are updated simultaneously. The MT88V32 supports separate analog (VEE) and digital (VDD) voltage references. This allows the user to select an optimum analog signal bias point.
Applications
· · · · High-end video routing and switching Medical instrumentation Automatic test equipment (ATE) Multi-me d i a communication
Y0-Y7
VDD VEE VSS X0 X1 X2 X3 Yi Xi
GND MR
8x4 "T" Switch Array
STROBE2
2nd Stage Latches I/O Control Logic R/W DATA CS T-Switch Configuration Address Decode GND
STROBE1
1st Stage Latches
AX0-AX1
AY0-AY2
Fi g u r e 1 - Functional Block Diagram
3-51
MT88V32
Preliminary Information
Y1 GND Y2 GND Y3 GND Y4 GND Y5 GND Y6
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 GND Y7 GND VEE IC* VDD VSS AX1 AX0 AY2 NC
GND Y0 GND GND X0 GND X1 GND X2 GND X3 GND NC MR STROBE2 STROBE1 R/W CS DATA AY0 AY1 NC * Connects toVEE
Figure 2 - Pin Connections
Pin Description
Pin #* 1, 3, 4, 6, 8, 10, 12, 14, 16, 18, 20, 39, 41, 43 2, 44, 42, 40 5, 7, 9, 11, 13, 15, 17, 19 21 22 23 24 25, 26 27, 30,31 28, 29 32 Name GND Description Analog Ground. Connect to system ground for crosstalk noise isolation. Pins 3 and 39 are not bonded internally.
X0, X1, X2, X3 Y0, Y1, Y2, Y3 Y4, Y5, Y6, Y7 VEE IC VDD VSS AX1,AX0 AY2-AY0 NC DATA
Analog Lines (input/output). Analog Lines (input/output).
33 34 35
CS R/W
Negative Analog Power Supply. Internal Connection. Positive Power Supply. Digital Ground Reference. X0-X3 I/O Address Select (inputs). Y0-Y7 I/O Address Select (inputs). No Connection. DATA (input/output). When input, a logic high will close the selected switch and a logic low will open the selected switch. When output, a logic high indicates a closed switch and a logic low indicates an opened switch. Chip Select (input). Active low. READ/WRITE Control (input). When high the DATA pin is an output (for reading from second stage latch); when low the DATA pin is an input (for writing to first stage latch).
36 37 38
STROBE1 STROBE 1 (input). Modifies memory content of first stage latch as determined by the addess and data lines, but does not change the switch array configuration of entire switch array. Active low. STROBE2 STROBE 2 (input). Transfers memory content of first stage latch to the second stage latch and hence, changes the configuration of entire switch array. Active low. MR MASTER RESET (input). Used to reset the first and second stage latches. Active low. NC No Connection.
3-52
Preliminary Information
Functional Description
The state of the MT88V32 8 X 4 switching matrix is updated through a simple parallel processor interface. This interface provides access to 32 two stage latches, which determines the state (open/ close) of each switching array node. Each latch (or node) is addressed by the AX0-AX1 and AY0-AY2 inputs as per Table 2, and the DATA input will deter mine if the connection is to be made (DATA=1) or opened (DATA=0). The second stage of the two stage latches controls the current state of each switching node. The value held in the first stage is the input to the second stage. This allows the device to be programmed in two ways. That is, individual switching nodes may be updated one at a time, or all nodes may be updated at once. To update one node at a time the STROBE2 input should be held low. This makes the second stage latches transparent and the matrix immediately reflects the state of the first stage latches. A write cycle example follows: 1) 2) 3) 4) 5) STROBE2 is low, CS and R/W are low, MR is high, AX0-AX1 and AY0-AY2 as per Table 2, DATA input high to close or low to open, and STROBE1 toggled from high-to-low-to-high.
MT88V32
These steps (one write cycle) may be repeated for each switch state change. This can also be accomplished by holding STROBE1 low and toggling STROBE2. See Figure 14 for timing. To update all nodes simultaneously all switch state changes must be written into the first stage latches. This is accomplished by holding STROBE2 high and perfor ming steps 2) through 5) above for each switching node that is to be changed. Writing to the first stage latches only will not affect the switching state of the matrix. When the changes have been made all the switches of the matrix may be updated simultaneously by toggling the STROBE2 input from high-to-low-to high. When STROBE2 is used to update the state of the MT88V32 all switch "breaks" are completed before any switch "makes" occur. There is approximately 10ns delay between "breaks" and "makes". Both the first and second stage latches will be cleared when the master reset (MR) is taken from high-to-low. This will open all the switch nodes. The operation of MR is independent of CS, AX0-AX1, AY0-AY2 and R/W. The status of each switching array node (second stage latch) can be read through the bidirectional DATA pin. A read cycle example follows: 1) CS is low, R/W and MR are high, 2) AX0-AX1 and AY0-AY2 as per Table 2, and 3) DATA output high for closed or low for open.
STROBE2 DATA
MR
R/W
CS
DATA
STROBE1
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1
1 0 0 0 0 x x 0 0
0 1 0 1 0 1 1 x x x 0
1 0 1 0 0 0 0 1 1 1 0 x
1 1 1 1 1 1 0 01 0 x
No Change to 1st stage latch. 1st stage latch is loaded with data. 1st stage latch is transparent. S elected latch is cleared and set again (i.e., output follows input). 1st stage latch output is frozen. Output of 1st stage latch is transferred to output of 2nd stage latches. 2nd stage latch output is frozen. B oth 1st stage and 2nd stage latches are transparent. DATA becomes an output and reflects the contents of the 2nd stage latch addressed by AX0-AX1 and AY0-AY2. A ll crosspoints opened (data in 1st and 2nd stage latches are cleared).
0
1
1
1
1
1
Table 1 - Truth Tables
Note: x = don't care, 0 = logic "0" state, 1 = logic "1" state A logic 1 on DATA input closes a connection. A logic 0 on DATA input opens a connection. 3-53
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