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Details, datasheet, quote on part number:MT8910AE-1
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Datasheet text preview:
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CMOS ST-BUSTM FAMILY MT8910-1 Digital Subscriber Line Interface Circuit
Features
· · · · · · · · · · · · Compatibl e with ISDN U-Interface standard Over 40dB (@40 kHz) of loop attenuation Full duplex transmission over single twisted pair Advance d echo cancelling technology High performance 2B1Q line code Full activation/deactivation state machine QSNR and line attenuation diagnostics Frame and superframe synchronization On-chip 15 second timer Inser tion loss measurement test signal & quiet mode Mitel ST-BUS compatible Single 5V power supply
ISSUE 2
March 1997
O rd e r i n g Information MT8910-1AE 28 Pin PDIP MT8910-1AP 44 Pin PLCC -40°C to +85°C
Description
The MT8910-1 Digital Subscriber Line Interface Circuit (DSLIC) is designed to provide ISDN basic rate access (2B+D) at the U-interface. Full duplex digital transmission at 160 kbit/s on a single twisted pair is achieved using echo cancelling hybrid (ECH) technology. This, in conjunction with the high perfor mance 2B1Q line code, allows the DSLIC to meet the loop length requirements of the digital subscr iber loops at the U-interface over the entire non-loaded telephone loop plant. The MT8910-1 is compatible with the complete range of Mitel Semiconductor ISDN components through the use of the ST-BUS interface.
Applications
· · · · Pair gain system ISDN NT1 and NT2 DSL interface Digital PABX line cards and telephone sets Digital multiplexers and concentrators
DSTi CDSTi
Transmit Interface
Scrambler & Encoder
DAC and Tx Filter
+
Lout+
MRST F0b C4b SFb F0od MS0 MS1 NT/LT
Control Register
Jitter Compensator Framing & Maintenance Decision Feedback Equalizer
Linear Echo Canceller
NonLinear Compensator
-
Lout-
Tone Detector
TRANSMIT/ RECEIVE TIMING & CONTROL INTERFACE
2nd Order PDM ADC Status Register Quantizer FIR Digital Filter CDSTo DSTo Receive Interface Descrambler, Decoder & Diagnostics Timing Adaptation Circuit Bias & Voltage Ref.
Lin+ Lin-
VSS
AVSS
VDD
AVDD
OSC2
OSC1
TSTin
TSTout TSTen VRef VBias
Fi g u r e 1 - Functional Block Diagram
9-3
MT8910-1
TSTin AVSS NC Lout+ NC LoutLin+ LinVRef VBias NC 28 PIN PDIP
Fi gur e 2 - Pin Connections
Pin Description
Pin # Name
PDIP PLCC
Description Line Out Minus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal, biased at VBias. Line Out Plus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal, biased at VBias. Analog Ground. Tie to VSS. I/O Structure Test Input. When TSTen is high, TSTin is used as a source to all output drivers. Refer to "I/O Structure Test" in functional description for more details. Tie to VSS for normal operation.
1 2 3 4
1 3 5 6
LoutLout+ AVSS TSTin
5 6 7 8
8 12 13 14
CDSTi Control/Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D- and C-channels in Dual mode. Unused in Single mode and should be connected to VSS. DSTi VSS DSTo Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D-, C-, B1- and B2channels in Single mode. In Dual mode, only the B-channels are input. Ground. Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D-, C-, B1- and B2channels in Single mode. In Dual mode, only the B-channels are output. This output is placed in high impedance during the unused channel times.
9
15
CDSTo Control/Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D- and C- channels in Dual mode. It is placed in high impedance in Single mode, and during the unused channel times in Dual mode. F0od Delayed Frame Pulse Output. A 244 ns wide negative going pulse indicating the end of the active ST-BUS channel times of the device to allow for daisy-chaining of other ST-BUS devices. Active after channel 0 in Dual Port mode and Channel 3 in Single Port Mode.
10
16
11
18
TSTout I/O Structure Test Output. When TSTen is high, the TSTout provides the output of an XOR chain which is sourced from all digital inputs. Refer to "I/O Structure Test" in functional description for more details. Leave unconnected for normal operation. MS0 MS1 Mode Select 0. CMOS input. Refer to Table 1. Mode Select 1. CMOS input. Refer to Table 1.
12 13
9-4
19 20
TSTout MS0 MS1 NT/LT TSTen SFb NC C4b NC F0b NC 44 PIN PLCC
LoutLout+ AVSS TSTin CDSTi DSTi VSS DSTo CDSTo F0od TSTout MS0 MS1 NT/LT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Lin+ LinVRef VBias AVDD IC VDD MRST OSC1 OSC2 F0b C4b SFb TSTen
NC CDSTi NC NC NC DSTi VSS DSTo CDSTo F0od NC
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28
NC AVDD NC NC NC IC VDD MRST OSC1 OSC2 NC
MT8910-1
Pin Description (continued)
Pin # Name
PDIP PLCC
Description NT/LT Mode Select. CMOS Input. When high, the DSLIC is setup in NT mode. When low, LT mode is selected.
14 15
21 22
NT/LT
TSTen I/O Structure Test Enable Input. This active high input enables the built-in test of all digital input and output structures. Refer to "I/O Structure Test" in functional description for more details. Tie to VSS for normal operation. SFb Superframe Pulse. In LT mode, an input pulse once every superframe (12 ms) which, when low during a falling edge of C4b within an F0b low pulse, sets the transmit superframe boundary. In NT mode, a 244 ns wide output pulse once every 12 ms indicating the boundary of the transmit superframe. In NT mode, the superframe timing is generated from the line signal time base and, as such, SFb will only be valid once the transceiver has achieved full activation.
16
23
17 18
25 27
C4b F0b
4096 kHz Data Clock. In LT mode, a 4096 kHz ST-BUS clock input. In NT mode, a 4096 kHz ST-BUS clock output frequency locked to the line signal. Frame Pulse. In LT mode, an 8 kHz input pulse indicating the start of the active ST-BUS channel times. In NT mode, an 8 kHz output pulse extracted from the line signal indicating the start of the active ST-BUS channel times. Oscillator Output. When the MT8910-1 operates with an External Clock (typically LT mode) connect OSC2 to the output of an external inverter providing a 10.24 MHz ±5ppm clock (see "10.24 MHz Clock Interface" section). When operating with a crystal (typically NT mode) connect one lead of the fundamental mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).
19
30
OSC2
20
31
OSC1
Oscillator Input. When the DSLIC operates with an External Clock (typically LT mode) connect OSC1 to the input of an external inverter (see Fig.11). When operating with a crystal (typically NT mode) connect the other lead of the fundamental mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).
21 22 23 24 25 26 27 28
32 33 34 38 41 42 43 44
2,4,7, 9 -11, 17,24 26,28 29,35 36,37 39,40
MRST VDD IC AVDD VBias VRef LinLin+ NC
Master Reset. Active low CMOS input performs a master reset of the DSLIC. Power Supply Input. Internal Connection. Leave unconnected. Analog Power Supply. Connect to VDD. Bias Voltage. Decouple to AVSS through a 1.0 µF ceramic capacitor. Reference Voltage. Decouple to AVSS through a 1.0 µF ceramic capacitor. Line Signal Input Minus. Internally biased at VBias. Line Signal Input Plus. Internally biased at VBias. No Connection. Leave circuit open.
9-5
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