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Details, datasheet, quote on part number:MT8920BP
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| Part: | MT8920BP |
| Category: | Communication => Network => TSI (Time Slot Interchange) => TDM/TSI Switches, Specialized (H.100, Backplane In |
| Description: | Description = 32 Channels TDM (ST-BUS) to Parallel Bus Access Circuit ;; Package Type = PLCC ;; No. Of Pins = 28 |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT8920BP datasheet File size : 593 kB |
| Request For quote: | Find where to buy MT8920BP
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Datasheet text preview:
MT8920B
ST-BUS Parallel Access Circuit Data Sheet
Features
· · · · · Hi g h speed parallel access to the serial ST-BUS P a ra l l el bus optimized for 68000 µP (mode 1) Fa s t dual-port RAM access (mode 2) Access time: 120 nsec P a ra l l el bus controller (mode 3) - no external controller required Fl e x i b l e interrupt capabilities - two independent/programmable interrupt sources with auto-vectoring S e l ec ta b l e 24 and 32 channel operation P ro g ra m ma b l e loop-around modes L ow power CMOS technology The ST-BUS Parallel Access Circuit (STPA) provides a simple interface between Zarlink's ST-BUS and parallel system environments. Orde ri ng Information M T 8 92 0B E 28 Pin Plastic DIP M T 8 92 0B P 28 Pin Plastic J-Lead M T 89 2 0 B S 28 Pin SOIC -40°C to 85°C
ISSUE 8 October 2002
Description
· · ·
Applications
· · · · · P a ra l l el control/data access to T1/CEPT digital trunk interfaces Di g i ta l signal processor interface to ST-BUS Co m p u te r to Digital PABX link Vo i c e store and forward systems In t e rp ro c e s s o r communications
D7-D0 A4-A0
T x0 Dual Port Ram 32 X 8
Parallelto-serial Converter
STo0
CS DS, OE R/W, WE DTACK, BUSY, DCS IRQ, 24/32 IACK, MS1 A5, STCH MM S Parallel Por t Interface
Interrupt Registers Control Registers
Rx0 Dual Port Ram 32 X 8
Serial-toP arallel Converter
STi0
T x1 Dual Port Ram 32 X 8
Parallelt o -S e ri a l Converter Comp/ MUX Addres s G enerat or
STo1
F0i C4i
VSS
VDD
F ig ure 1 - Functional Block Diagram 1
MT8920B
STi0 IACK, MS1 F0i C4i VDD MM S DTACK, BUSY, DCS
Data Sheet
28 PIN PDIP/SOIC
Fi gu re 2 - Pin Connections
Pin Description
Pin # 1 2 Na m e C4 i F0i Description 4.096 MHz Clock. The ST-BUS timing clock used to establish bit cell boundaries for the serial bus. Framing Pulse. A low going pulse used to synchronize the STPA to the 2048 kbit/s ST-BUS stream. The first falling edge of C4i subsequent to the falling edge of F0i identifies the start of a frame. Interrupt Acknowledge (Mode 1). This active low input signals that the current bus cycle is an interrupt vector fetch cycle. Upon receiving this acknowledgement, the STPA will output a user-programmed vector number on D0 - D7 indicating the source of the interrupt. Mode Select 1 (Mode 2,3). This input is used to select the device operating modes. A low applied to this pin will select mode 3 while a high will select mode 2. (Refer to Table 1.) ST-BUS Input 0. This is the input for the 2048 kbit/s ST-BUS serial data stream. Chip Select. This active low input is used to select the STPA for a parallel access . Data Strobe (Mode 1). This active low input indicates to the STPA that valid data is on the data bus during a write operation or that the STPA must output valid data on the data bus during a read operation. Output Enable (Mode 2). This active low input enables the data bus driver outputs. Output Enable (Mode 3). This active low output indicates that the selected device is to be read and that the data bus is available for data transfer. Read/Write (Mode 1,2). This input defines the data bus transfer as a read (R/W = 1) or a write (R/W= 0) cycle. Write Enable (Mode 3). This active low output indicates the data on the data bus is to be written into the selected location of an external device.
3
IACK
MS1 4 5 6 STi0 CS DS
OE OE 7 R/W WE 8-12
A0-A4 Address Bus (Mode 1,2). These inputs are used to select the internal registers and two-port memories of the STPA. A0-A4 Address Bus (Mode 3). These address outputs are generated by the STPA and reflect the position in internal RAM where the information will be fetched from or stored in. Addresses generated in this mode are used to access external devices for direct memory transfer.
2
A4 A5, STCH VSS D0 D1 D2 D3
C4i F 0i IACK, MS1 STi0 CS DS, OE R/W, WE A0 A1 A2 A3 A4 A5, STCH VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD MM S DTACK, BUSY, DCS IRQ, 24/32 ST o1 ST o0 D7 D6 D5 D4 D3 D2 D1 D0
4 3 2 1 28 27 26 ·
12 13 14 15 16 17 18
CS DS, OE R/W, WE A0 A1 A2 A3
5 6 7 8 9 10 11
25 24 23 22 21 20 19
IRQ, 24/32 ST o1 ST o0 D7 D6 D5 D4
28 PIN J-LEAD
Data Sheet
Pin Description (continued)
Pin # 13 Na m e A5 A5 Description
MT8920B
Address Bit A5 (Mode 1). This input is used to extend the address range of the STPA. A5 selects internal registers when high and Tx/Rx RAM's when low. Address Bit A5 (Mode 2). This input is used to extend the address range of the STPA. A5 selects Tx0/Rx0 RAM's when low and Tx1/Rx0 RAM's when high.
STCH Start of Channel (Mode 3). This signal is a low going pulse which indicates the start of an ST-BUS channel. The pulse is four bits wide and begins at the start of each valid channel. 14 15-22 23 24 VSS Ground. D0-D7 Bidirectional Data Bus. This bus is used to transfer data to or from the STPA during a write or read operation. STo0 STo1 ST-BUS Output 0. This output supplies the output ST-BUS 2048 kbit/s serial data stream from Tx0 two-port RAM. ST-BUS Output 1. In modes 1 and 2 this output supplies the output ST-BUS 2048 kbit/s serial data stream from Tx1 two-port RAM. In mode 3, information arriving at STi0 is output here with one frame delay. Interrupt Request (Mode 1). This open drain output, when low, indicates when an interrupt condition has been raised within the STPA. 24 Channel/32 Channel Select (Mode 2,3). This input is used to select the channel configuration in modes 2 and 3. A low applied to this pin will select a 24 (T1) channel mode while a high will select a 32 (CEPT) channel mode.
25
I RQ 24/32
26
DTACK Data Transfer Acknowledge (Mode 1). This open drain output is supplied by the STPA to acknowledge the completion of data transfers back to the µP. On a read of the STPA, DTACK low indicates that the STPA has put valid data on the data bus. On a write, DTACK low indicates that the STPA has completed latching the µP's data from the data bus. BUSY BUSY (Mode 2). This open drain output signals that the controller and the ST-BUS are accessing the same location in the dual-port RAM's. It is intended to delay the controller access until after the ST-BUS completes its access. DCS Delayed Chip Select (Mode 3). This low going pulse, which is four bit cells long, is active during the last half of a valid channel. This signal is used to daisy-chain together two STPA's in mode 3 that are accessing devices on the same parallel data bus. Master Mode Select (Reset). This Schmitt trigger input selects between either mode 1 (MMS = 1), or modes 2and 3 (MMS = 0). If MMS is pulsed low in Mode 1 operation the control and interrupt registers will be reset. (Refer to Table 1.) During power-up, the time constant of the reset circuit (see Fig. 8) must be a minimum of five times the rise time of the power supply.
27
MMS
28 VDD Power Supply Input. (+5V). Pin Descriptions pertain to all modes unless otherwise stated.
Mo d e M MS MS1 Mode of Operation Function
1
1
N/A
µP Peripheral Mode
Fast RAM Mode
The STPA provides parallel-to-serial and serial-to-parallel conversions through a 68000-type interface. Two Tx RAMs and one Rx RAM are available along with full interrupt capability. 32 channel or 24 channel support is available. Control Register 1, bit D5 (RAMCON) = 0 for 32 channel operation and D5 (RAMCON)= 1 for 24 channel operation. The STPA provides a fast access interface to Tx0, Tx1 and Rx0 RAMs. This mode is intended for full parallel support of 24 channel T1/ESF trunks and 32 channel CEPT trunks. Input 24/32 (pin 25) = 0 for 24 channel operation, input 24/32 (pin 25) = 1 for 32 channel operation. The STPA will synchronously drive the parallel bus using the address generator and provide all data transfer signals. This mode is intended to support 24 or 32 channel devices in the absence of a parallel bus controller. Input 24/32 (pin 25) = 0 for 24 channel operation, input 24/32 (pin 25) = 1 for 32 channel operation.
2
0
1
3
0
0
Bus Controller Mode
Ta bl e 1. STPA Modes of Operation 3
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