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Details, datasheet, quote on part number:MT8982ASR
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Datasheet text preview:
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ISO-CMOS ST-BUSTM FAMILY MT8982 Small Digital Switch (MiniDX)
Features
· · · · · · · · ST-BUS/ G C I compatible switch matrix 64 channel non-blocking time switch 2 x 32 channel serial inputs and outputs Per-chan n e l tristate control 4-pin serial microprocessor interface Patented message mode Low power consumption (10 mW) Single 5 volt supply
ISSUE 6
May 1995
O rd e r i n g Information MT8982AE 16 Pin Plastic DIP MT8982AS 1 6 Pin SOIC MT8982AN 2 0 Pin SSOP -40 to +85°C
Description
The MT8982 Small Digital Switch (MiniDX) is a nonblocking CMOS time switch with a capacity of up to 64 - 8 bit Time Division Multiplexed (TDM) encoded voice or data channels. It is a size-optimized version of MITEL's successful MT8980D Digital Switches, providing switching capability in cost sensitive applications such as telephone sets and digital key systems. The TDM interface to the device is via two pairs of 2048 kbit/s serial streams with 32 64 kbit/s channels per stream (ST-BUS). A serial microport provides access to the device for programming the required connections. The serial microport is compatible with most common microcontrollers. The unique message mode capability allows the MT8982 to act as a controller for other members of MITEL's ST-BUS family of components.
Applications
· · · · · · Cost sensitive digital switching applications Digital key telephone systems GCI/ST-BU S conversion ST-BUS device control interface ISDN telephone set support circuit Inter proce s s o r communication
STi0 STi1
Serial to Parallel Conver ter
64 x 8 Data Memory
Output Mux
Parallel to Serial Conver ter
STo0 STo1
F0i C4i F0o Address Counters
Address Mux
Data Mux RxD/CSTi0 TxD/NC SCLK/CSTi1 CS/CMS MPS Address Mux ODE Serial Micropor t 64 x 9 Connect Memory 3-State Control
Fi gur e 1 - Functional Block Diagram
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MT8982
ISO-CMOS
STi0 STi1 STo0 STo1 RxD/CSTi0 TxD/NC SCLK/CSTi1 VSS
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD ODE IC MPS F0o F0i C4i CS
STi0 STi1 NC STo0 STo1 RxD/CSTi0 TxD/NC NC SCLK/CSTi1 VSS
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD ODE IC MPS F0o NC F0i NC C4i CS
16 PIN PLASTIC/SOIC
20 PIN SSOP
Fi gure 2 - Pin Connections
Pin Description
Pin # Name 16 1-2 3-4 5 20 1-2 4-5 6 STi0STi1 STo0STo1 RxD/ CSTi0 Serial TDM Input 0 and 1 (Inputs). 2048 kbit/s input data streams containing 32 8-bit channels synchronized to F0i. Serial TDM Output 0 and 1 (Outputs). 2048 kbit/s output data streams containing 32 8-bit channels synchronized to F0i. Received Data/Control Stream Input 0 (Input). When MPS is low, this pin receives serial micropor t data clocked in by the rising edge SCLK. When MPS is high, this pin receives a 2048 kbit/s serial TDM stream containing 32 8-bit channels, which are written into the Connect Memory locations corresponding to STo0. Transmit Data (Output). When MPS is low, serial microport data is clocked out on this pin by the falling edge of SCLK. When MPS is high this output is disabled. Serial Microport Clock/Control Stream Input 1 (Input). When MPS is low, this pin receives a clock which is used to clock data to/from a microcontroller via a serial microport. When MPS is high, this pin receives a 2048 kbit/s serial TDM stream containing 32 8-bit channels, which are written into the Connect Memory locations corresponding to STo1. Power Input. Negative supply (ground). Chip Select (Input). When MPS is low, a low on this pin enables the serial microport. A high on this pin disables RxD and tristates TxD. When MPS is high, this pin must be low. Serial TDM Clock (Input). This clock input is used to clock the TDM data into and out of the device and refreshes the internal dynamic RAM. The clock rate is 4.096 MHz and data is clocked in on the rising edge of C4i three-quarters of the way through a bit period. Frame Pulse (Input). This input is the frame synchronization pulse for the 2048 kbit/s serial TDM streams. It may be either active low stradling the frame boundary (ST-BUS) or active high at the beginning of timeslot 5 (GCI). Frame Pulse (Output). This pin outputs a frame pulse in the opposite format to F0i (GCI or ST-BUS) delayed or advanced by five channels. Microport Select (Input). When this pin is held low, the serial microport is in normal mode. When this pin is high, the microport is in serial bus mode. Internal Connection. Tie to VSS for normal operation. Output Drive Enable (Input). When this pin is held high, the STo0 and STo1 output drivers function normally. When this pin is low, STo0 and STo1 are tristated. NB: When ODE is high, individual channels on STo0 and STo1 can be tristated under software control. Power Input. Positive supply. No Connection. Description
6 7
7 9
TxD SCLK/ CSTi1
8 9 10
10 11 12
VSS CS C4i
11
14
F0i
12 13 14 15
16 17 18 19
F0o MPS IC ODE
16
20
3,8, 13,15
VDD NC
2-32
ISO-CMOS
F u n ction a l Description
The MT8982 (MiniDX) provides cost effective time switching capability for small size applications utilizing up to two serial Time Division Multiplexed (TDM) streams. Each TDM stream consists of 32 64 kb/s channels, giving the MiniDX a maximum capacity of 64 channels. The input framing signal may be either a ST-BUS or a GCI frame pulse. The MT8982 will output a delayed or advanced frame pulse in the opposite format to permit conversion between the two formats. The MiniDX can switch data from any channel in one of the two serial input TDM streams to any channel in either of the two serial output TDM streams. The microcontroller controlling the MiniDX writes to the MT8982 Connect Memory to establish the connection between the required input TDM channel and the selected output TDM channel(s). By reading the Connect Memory the microcontroller can check switched connections which have already been established. The MiniDX can also operate in message mode where the microcontroller transmits the data on the TDM serial stream. The microcontroller writes to the MT8982 Connect Memory to transmit data on the required output TDM channels. Reading the Data Memor y of the MT8982 allows the microcontroller to receive messages from TDM input channels. These operations are useful for control of other ST-BUS components or for interprocessor communication.
MT8982
for matted frame pulse is active high at the beginning of timeslot 5 (relative to the MT8982) and idles low. The MT8982 automatically determines the type of frame pulse from the level of the idle over five clock per iods. A ST-BUS formatted frame pulse resets the inter nal address counters to zero. A GCI formatted frame pulse resets the counters to five. F0o outputs a frame pulse in the opposite format. If F0i is a ST-BUS formatted frame pulse, F0o will be a GCI formatted frame pulse delayed by five channels after F0i. If F0i is a GCI formatted frame pulse, F0o will be a ST-BUS formatted frame pulse delayed by 27 channels (32-5). Dur ing normal operation every second falling edge of the clock marks a timeslot boundary and the input data is clocked in by the rising edge, three-quarters of the way into the bit cell. The master clock must be 4.096 MHz for the F0o signal to be valid and to receive a GCI formatted F0i. Data which is output onto a TDM serial output channel may come from two sources; the Data Memor y or the Connect Memory. If a channel is configured in connection mode, the source of output data is the Data Memory. If a channel is configured in message mode, the source of the output data is the Connect Memory. Data destined for a particular channel on the serial output links is read from the data or connect memory in the previous channel timeslot. This allows for delay in RAM access and parallel-to-ser ial conversion. Each output data channel can also be placed in tristate mode. When an output channel is in connection mode, the TDM output data is read from a Data Memory location pointed to by an address stored in the 64x8 bit Connect Memory. The Connect Memory locations are addressed sequentially, with each location corresponding to an output TDM link/ channel. In the channel time before the data is to be output, the contents of each Connect Memory location are output to the address bus of the Data Memor y. The contents of the Data Memory at the selected address are then transferred to the parallelto-ser ial converter. The parallel-to-serial converter outputs onto the TDM serial stream during the correct channel time. By having the output channel specify the input channel, the user can route the same input channel to several output channels. This function is useful for broadcasting or resource channel uses.
Hardware Description
TDM Interface The MT8982 continuously receives TDM serial data at 2048 kbit/s through two serial inputs. These serial streams are then converted into a parallel format and stored sequentially in a 64x8 bit Data Memory. The sequential addressing is generated by an internal counter that is reset by the input 8 kHz frame pulse (F0i) which marks the frame boundaries of the incoming serial data stream. This counter increments with each timeslot so that it matches the binary count of the timeslot of the incoming data. The TDM timeslot count always corresponds to the ST-BUS channel positions. An extra address bit is used to differentiate between the two input data streams. The input 8 kHz frame pulse may be either ST-BUS or GCI formatted. A ST-BUS formatted frame pulse is an active low signal which straddles the frame boundar y. It idles high the rest of the time. A GCI
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