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Details, datasheet, quote on part number:MT8985
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| Part: | MT8985 |
| Category: | Logic => Switches |
| Description: | 256 X 256 Channels (8 TDM Streams at 2.048 Mbps) Non-blocking Enhance Digital Switch (EDX) With Constant Delay Mode |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT8985 datasheet File size : 691 kB |
| Request For quote: | Find where to buy MT8985
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Datasheet text preview:
CMOS ST-BUS FAMILY MT8985 Enhanced Digital Switch
Features
· · · · · · · · · 256 x 256 channel non-blocking switch Program m a bl e frame integrity for wideband channels Automatic identification of ST-BUS/GCI interface backplanes Per channel tristate control Patented message mode Non-mult i p l exe d microprocessor interface Single +5 volt supply Available in DIP-40, PLCC-44 and QFP-44 packages Pin compatible with MT8980 device
DS5408
ISSUE 5
March 1997
Ordering Information MT8985AE 4 0 Pin Plastic DIP MT8985AP 4 4 Pin PLCC MT8985AL 4 4 Pin QFP -40°C to +85°C
Description
The MT8985 Enhanced Digital Switch device is an upgraded version of the popular MT8980D Digital Switch (DX). It is pin compatible with the MT8980D and retains all of the MT8980D's functionality. This VLSI device is designed for switching PCM-encoded voice or data, under microprocessor control, in digital exchanges, PBXs and any ST-BUS/MVIP environment. It provides simultaneous connections for up to 256 64kb/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s stream. As the main function in switching applications, the device provides per-channel selection between variable or constant throughput delays. The constant throughput delay feature allows grouped channels such as ISDN H0 to be switched through the device maintaining its sequence integrity. The MT8985 is ideal for medium sized mixed voice/data switch and voice processing applications.
Applications
· · · · · · Medium size digital switch matrices Hypercha n n e l switching (e.g., ISDN H0) ST-BUS/ MV I PTM interface functions Ser ial bus control and monitoring Centralize d voice processing systems Data multiplexer
C4i
F0i
VDD
VSS
ODE
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 Serial to Parallel Conver ter Data Memory
Frame Counter
Output MUX Parallel to Serial Conver ter
STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7
Control Register Connection Memory Control Interface
DS CS R/W A5/ A0
DTA D7/ D0
CSTo
Figure 1 - Functional Block Diagram
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MT8985
NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 A3 A4 A5 DS R/W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 CSTo ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 D5 D6 D7 CS 40 PIN PLASTIC DIP
STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2
NC A3 A4 A5 DS R/W CS D7 D6 D5 NC
44 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
40 DIP 44 44 PLCC QFP
Name
Description
1 2-9 10 11
2
40
DTA
Data Acknowledgement (Open Drain Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output.
3-5 41-43 STi0- ST-BUS Input 0 to 7 (Inputs). Serial data input streams. These streams have 32 7-11 1-5 STi7 channels at data rates of 2.048 Mbit/s. 12 13 6 7 VDD F0i +5 Volt Power Supply rail. Frame Pulse (Input): This input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as ST-BUS and GCI. Clock (Input). 4.096 MHz serial clock for shifting data in and out of the data streams.
12
14
8
C4i
13-18 15-17 9-11 A0-A5 Address 0 to 5 (Inputs). These lines provide the address to MT8985 internal 19-21 13-15 registers. 19 22 16 DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. Read/Write (Input). This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
20
23
17
R/W
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NC A3 A4 A5 DS R/W CS D7 D6 D5 NC 44 PIN QFP
12 13 14 15 16 17 18 19 20 21 22
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28
MT8985
Pin Description
Pin #
40 DIP 44 44 PLCC QFP
Name
Description
21
24
18
CS
Chip Select (Input). Active low input enabling a microprocessor read or write of control register or internal memories.
22-29 25-27 19-21 D7-D0 Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to data 29-33 23-27 in the internal control register, connect memory high, connect memory low and data memory. 30 34 28 VSS Ground Rail. 31-38 35-39 29-33 STo7- ST-BUS Outputs 7 to 0 (Three-state Outputs). Serial data output streams. These 41-43 35-37 STo0 streams are composed of 32 channels at data rates of 2.048 Mbit/s. 39 44 38 ODE Output Drive Enable (Input). This is an output enable for the STo0 to STo7 serial outputs. If this input is low STo0-7 are high impedance. If this input is high each channel may still be put into high impedance by software control. CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit in the Connect Memory high locations. NC No Connection.
40
1
39
6, 18, 12,22 28, 34, 40 44
Functional Description
With the integration of voice, video and data services into the same network, there has been an increasing demand for systems which ensure that data at N x 64 Kbit/s rates maintain frame sequence integrity while being transported through time slot interchange circuits. Existing requirements demand time slot interchange devices performing switching with constant throughput delay while guaranteeing minimum delay for voice channels. The MT8985 device provides both functions and allows existing systems based on the MT8980D to be easily upgraded to maintain the data integrity while multiple channel data are transported. The device is designed to switch 64 kbit/s PCM or N x 64 kbit/s data. The MT8985 can provide both frame integrity for data applications and minimum throughput switching delay for voice applications on a per channel basis. By using Zarlink Message mode capability, the microprocessor can access input and output time slots on a per channel basis to control devices such as the Zarlink MT8972, ISDN Transceivers and T1/ CEPT trunk interfaces through the ST-BUS interface. Different digital backplanes can be accepted by the MT8985 device without user's intervention. The MT8985 device provides an internal circuit that
automatically identifies the polarity and format of frame synchronization input signals compatible to ST-BUS and GCI interfaces. Device Operation A functional block diagram of the MT8985 device is shown in Figure 1. The serial ST-BUS streams operate continuously at 2.048 Mb/s and are arranged in 125 µs wide frames each containing 32 8-bit channels. Eight input (STi0-7) and eight output (STo0-7) serial streams are provided in the MT8985 device allowing a complete 256 x 256 channel nonblocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz, as required in ST-BUS and GCI specifications. Data Memory The received serial data is converted to parallel for mat by the on-chip serial to parallel converters and stored sequentially in a 256-position Data Memor y. The sequential addressing of the Data Memor y is generated by an internal counter that is reset by the input 8 kHz frame pulse (F0i) marking the frame boundaries of the incoming serial data streams. Depending on the type of information to be switched, the MT8985 device can be programmed to perform
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