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Details, datasheet, quote on part number:MT8986AE
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| Part: | MT8986AE |
| Category: | Communication => Network => TSI (Time Slot Interchange) => TDM/TSI Switches, Blocking |
| Description: | Description = 512 X 256 Channels Multiple Rate Digital Switch (MRDX) With Constant Delay Mode ;; Package Type = Pdip ;; No. Of Pins = 40 |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT8986AE datasheet File size : 697 kB |
| Request For quote: | Find where to buy MT8986AE
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Datasheet text preview:
CMOS ST-BUS FAMILY MT8986 Multiple Rate Digital Switch
Features
· · · · · · · · · · · 256 x 256 or 512 x 256 switching configurations 8-bit or 4-bit channel switching capability Guarante e s frame integrity for wideband channels Automatic identification of ST-BUS/GCI interfaces Accepts serial streams with data rates up to 8.192 Mb/s Rate conversion from 2.048 Mb/s to 4.096 or 8.192 Mb/s and vice-versa Program m a bl e frame offset on inputs Per-chan n e l three-state control Per-chan n e l message mode Control interface compatible to Intel/Motorola CPUs Low power consumption
ISSUE 4
March 1997
Ordering Information MT8986AE 40 Pin Plastic DIP MT8986AP 44 Pin PLCC MT8986AL 4 4 Pin QFP -40°C to +85°C
Description
The Multiple Rate Digital Switch (MRDX) is an upgraded version of Zarlink's MT8980D Digital Switch (DX). It is pin compatible with the MT8980D and retains all of its functionality. This device is designed to provide simultaneous connections (nonblocking) for up to 256 64kb/s channels or blocking connections for up to 512 64kb/s channels. The serial inputs and outputs connected to MT8986 may have 32 to 128 64kb/s channels per frame with data rates ranging from 2048 up to 8192 kb/s. The MT8986 provides per-channel selection between variable and constant throughput delays allowing voice and grouped data channels to be switched without corrupting the data sequence integrity. In addition, the MT8986 can be used for switching of 32 kb/s channels in ADPCM applications. The MT8986 is ideal for medium size mixed voice and data switching/processing applications.
VDD VSS ODE
Applications
· · · · · · · Medium size digital switch matrices Hypercha n n e l switching (e.g., ISDN H0) MVIPTM interface functions Ser ial bus control and monitoring Centralize d voice processing systems Voice/Da t a multiplexer 32 kbit/s channel switching
* * * * * *
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15
Serial to Parallel Conver ter Timing Unit
Multiple Buffer Data Memory
Output MUX Parallel to Serial Conver ter Connection Memory
Internal Registers
Microprocessor Interface
STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 * STo9 *
* 44 Pin only
CLK FR AS/ IM ALE *
DS CS RD
R/W A0/ DTA AD7/ AD0 WR A7
CSTo
Figure 1 - Functional Block Diagram
2-63
MT8986
AS/ALE STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 STi4/STo8 AS/ALE STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 STi4/STo8 STo3 STo4 STo5 STo6/A6 STo7/A7 VSS AD0 AD1 AD2 AD3 AD4 STi3 STi4 STi5 STi6/A6 STi7/A7 VDD FR CLK STi8/A0 STi9/A1 STi10/A2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 STo3 STo4 STo5 STo6/A6 STo7/A7 VSS AD0 AD1 AD2 AD3 AD4 DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6/A6 STi7/A7 VDD FR CLK A0 A1 A2 A3 A4 A5 DS/RD R/W\WR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 PIN DIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 CSTo ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6/A6 STo7/A7 VSS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 CS
STi3 STi4 STi5 STi6/A6 STi7/A7 VDD FR CLK STi8/A0 STi9/A1 STi10/A2
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 IM STi11/A3 STi12/A4 STi3/A5 DS/RD R/W/WR CS AD7 AD6 AD5 STi15/STo9
44 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
40 DIP 44 PLCC 44 QFP
Name DTA
Description Data Acknowledgement (Open Drain Output). This active low output indicates that a data bus transfer is complete. A 10k pull-up resistor is required at this output.
1
2
40
2-7
3-5 7-9
41-43 1-3
STi0-5 ST-BUS Inputs 0 to 5 (Inputs). Serial data input streams. These streams may have data rates of 2.048, 4.096 or 8.192 Mbit/s with 32, 64 or 128 channels, respectively.
2-64
IM STi11/A3 STi12/A4 STi3/A5 DS/RD R/W/WR CS AD7 AD6 AD5 STi15/STo9 44 PIN QFP
12 13 14 15 16 17 18 19 20 21 22
MT8986
Pin Description (continued)
Pin #
40 DIP 44 PLCC 44 QFP
Name
Description
8
10
4
STi6/A6 ST-BUS Input 6/Addr.6 input (Input). The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is used along with a higher input rate of 8.192 or 4.096 Mb/s, this pin provides A6 address input function. For 2.048 and 4.096 Mb/s (8x4) applications or when multiplexed CPU bus (44 pin only) is selected, this pin assumes STi6 function. See Control Register bits description and Tables 1, 2, 6 & 7 for more details. Note that for applications where both A6 and STi6 inputs are required simultaneously (e.g., 8 x 4 switching configuration at 4.096 Mb/s or rate conversion between 2.048Mb/s to 4.196 or 8.192 Mb/s) the A6 input should be connected to pin STo6/A6. STi7/A7 ST-BUS Input 7/Addr.7 input (Input): The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is used along with a higher input rate of 8.192 Mb/s, this pin provides A7 address input function. For 2.048 and 4.096 Mb/s (8x4) applications or when multiplexed CPU bus (44 pin only) is selected, this pin assumes STi7 function. See Control Register bits description and Tables 1, 2, 6 & 7 for more details. Note that for applications where both A7 and STi7 inputs are required simultaneously (e.g., 2.048 to 8.192 Mb/s rate conversion) the A7 input should be connected to pin STo7/A7. VDD FR +5 Volt Power Supply. Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI interface specifications. Clock (Input). Serial clock for shifting data in/out on the serial streams. Depending on the serial interface speed selected by IMS (Interface Mode Select) register, the clock at this pin can be 4.096 or 8.192 MHz.
9
11
5
10 11
12 13
6 7
12
14
8
CLK
13-15 15-17 9-11
A0-2/ Address 0-2 / Input Streams 8-10 (Input). When non-multiplexed CPU bus is STi8-10 selected, these lines provide the A0-A2 address lines to MT8986 internal registers. When 16x8 switching configuration is selected (in 44 pin only), then these pins are ST-BUS serial inputs 8 to 10 receiving data at 2.048 Mb/s. A3-5/ Address 3-5 / Input Streams 11-13 (Input). When non-multiplexed CPU bus is STi11-13 selected, these lines provide the A3-A5 address lines to MT8986 internal registers. When 16x8 switching configuration is selected (in 44 pin only), then these pins are ST-BUS serial inputs 11 to 13 receiving data at 2.048 Mb/s. DS/RD Data Strobe/Read (Input). When non-multiplexed CPU bus or Motorola multiplexed bus (44 pin only) are selected, this input is DS. This active high input works in conjunction with CS to enable read and write operation. For Intel/National multiplexed bus (44 pin only), this input is RD. This active low input configures the data bus lines (AD0-AD7) as outputs. R/W\WR Read/Write \ Write (Input). In case of non-multiplexed and Motorola multiplexed buses (44 pin only), this input is R/W. This input controls the direction of the data bus lines (AD0-AD7) during a microprocessor access. With Intel/National multiplexed timing (44 pin only), this input is WR. This active low signal configures the data bus lines (AD0-AD7) as inputs. CS AD7AD0 Chip Select (Input). Active low input enabling a microprocessor read or write of the control register or internal memories. Data Bus (Bidirectional): These pins provide microprocessor access to the internal control registers, connection memories high and low and data memories. In multiplexed bus mode (44 pin) these pins also provide the input address to the internal Address Latch circuit. Ground.
16-18 19-21 13-15
19
22
16
20
23
17
21
24
18
22-29 25-27 19-21 29-33 23-27
30
34
28
VSS
2-65
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