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Details, datasheet, quote on part number:MT90810AK
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| Part: | MT90810AK |
| Category: | Communication => Network => TSI (Time Slot Interchange) => TDM/TSI Switches, Blocking |
| Description: | Description = 256 X 128 Channels Flexible Mvip Interface Circuit (FMIC) ;; Package Type = PQFP ;; No. Of Pins = 100 |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT90810AK datasheet File size : 478 kB |
| Request For quote: | Find where to buy MT90810AK
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Datasheet text preview:
CMOS MT90810 Flexible MVIP Interface Circuit
Features
· · MVIP and ST-BUS compliant
ISSUE 3
March 1997
Ordering Information MT90810AK 100 Pin PQFP 0 °C to +70 °C
· · ·
· · · ·
MVIP Enhanced Switching with 384x384 channel capacity (256 MVIP channels; 128 local channels) On-chip PLL for MVIP master/slave operation Local output clocks of 2.048,4.096,8.192MHz with programmable polarity Local serial interface is programmable to 2.048, 4.096, or 8.192Mb/s with associated clock outputs Additiona l control output stream Per-chan n e l message mode Two independently programmable groups of up to 12 framing signals each Motorola non-multiplexed or Intel multiplexed/ non-mult i p l exe d microprocessor interface
Description
Zarlink's MT90810 is a Flexible MVIP Interface Circuit (FMIC). The MVIP (Multi-Vendor Integration Protocol) compliant device provides a complete MVIP compliant interface between the MVIP Bus and a wide variety of processors, telephony interfaces and other circuits. A built-in digital time-slot switch provides MVIP enhanced switching between the full MVIP Bus and any combination of up to 128 full duplex local channels of 64kbps each. An 8 bit microprocessor port allows real-time control of switching and programming of device configuration. On-board clock circuitry, including both analog and digital phase-locked loops, supports all MVIP clock modes. The local interface supports PCM rates of 2.048, 4.096 and 8.192Mb/s, as well as parallel DMA through the microprocessor port.
Applications
· · · · · Medium size digital switch matrices MVIP interface functions Ser ial bus control and monitoring Centralize d voice processing systems Voice/Da t a multiplexer
EX_8KA
EX_8KB
X2
X1/CLKIN PLL_LO
PLL_LI
FRAME
SEC8K
C4b C2o F0b DSo[0:7] DSi[0:7] LDO[0:3] LDI[0:3] TCK TMS TDI TDO
Timing and Clock Control (Oscillator and Analog & Digital PLLs) Enhanced Switch S-P/ P-S Data Memory Connection Memory Programmable Framing Signals
CLK2 CLK4 CLK8 RESET
CSTo FGA[0:11] FGB[0:11]
JTAG
Microprocessor Interface
ERR
AD[0:7] A[0:1] ALE
WR/ R/W
RD/ DS
CS
RDY/ DREQ[0:1] DACK[0:1] DTACK
Figure 1 - Functional Block Diagram
2-169
MT90810
SEC8K
FGB9
FGA9
FGA8
LDO0
FGB8
DSo1
DSo7
DSo6
DSo5
DSo4
DSo3
DSo2
DSo0
DSi1
DSi7
DSi6
DSi5
DSi4
DSi3
DSi2
DSi0
VDD
C4b
FGA10 LDO1 LDO2 FGB10 LDO3 VDD LDI0 LDI1 LDI2 LDI3 EX8_KA EX8_KB VSS FRAME CLK8 FGA11 CLK4 CLK2 FGB11 FGA0
80 82
78
76
74
72
70
68
66
64
62
60
58
56
C2o
54
52 50 48
FGB7
VSS
VSS
VSS
F 0b
DREQ1 DREQ0 DACK1 DACK0 FGA7 AD7 AD6 AD5 AD4 VSS VDD FGB6 AD3 AD2 AD1 AD0 A1 FGA6 A0 ERR
84 46 86 44 88 42 90 92 94 36 96 34 98 32 100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 40 38
100 PIN PQFP
FGA1
FGA2
FGA3
FGA4
FGB0
FGB1
FGB2
FGB3
TDI
TDO
TMS
FGB4
FGA5
WR/[R/W]
RD/[DS]
FGB5
Figure 2 - Pin Connections
Pin Description
Pin # 58, 60, 63, 67, 70, 72, 74, 77 59, 61, 64, 68, 71, 73, 75, 78 80, 82, 83, 85 87, 88, 89, 90 4 55 56 54 53 91 Name DSo[0:7] Description MVIP DSo Streams (Bidirectional CMOS). 2.048Mb/s serial data streams conforming to ST-BUS serial data stream specifications.
DSi[0:7]
MVIP DSi Streams (Bidirectional CMOS). 2.048Mb/s serial data streams conforming to ST-BUS serial data stream specifications.
LDO[0:3] LDI[0:3] CSTo F0b C4b C2o SEC8K EX_8KA
Local Output Serial Streams (Output). Serial data streams programmable to 2.048, 4.096 or 8.192Mb/s data rates. Local Input Serial Streams (TTL Input). Serial data streams programmable to 2.048, 4.096 or 8.192 Mb/s data rates. Control ST-BUS Output (Output). This is a 1.024Mb/s output. The state of each bit in this stream is determined by the CSTo bit in connection memory high. MVIP F0 signal (CMOS Input/Output). ST-BUS 8kHz framing signal MVIP C4 signal (CMOS Input/Output). ST-BUS 4.096MHz clock MVIP C2 signal (Output). ST-BUS 2.048MHz clock. This pin is automatically set to high impedance when it is not driven. MVIP SEC8K signal (CMOS Input/Output). A secondary 8kHz signal used either as an input source to the on-chip digital PLL or as an output to the MVIP bus. External 8kHz input A (TTL Input).
2-170
RDY/[DTACK]
RESET
VSS
TCK
VCO_VSS
CSTo
X2
X1/CLKIN
VDD
PLL_LO
PLL_LI
VCO_VDD
ALE
CS
MT90810
Pin Description (continued)
Pin # 92 94 95 97 98 100, 1, 2, 3, 5, 20, 33, 46, 57, 69, 81, 96 6, 7, 8, 9, 14, 28, 39, 51, 62, 76, 84, 99 19 35, 36, 37, 38, 42, 43, 44, 45 32, 34 Name EX_8KB FRAME CLK8 CLK4 CLK2 FGA[0:11] External 8kHz input B (TTL Input). Local Frame Output Signal (Output). This 8kHz framing signal has a duty cycle and period equal to the MVIP F0 signal. 8MHz Local Output Clock (Output). This is a 8MHz clock. 4MHz Local Output Clock (Output). This 4MHz clock has a duty cycle and period equal to the MVIP C4 signal. 2MHz Local Output Clock (Output). This 2MHz clock has a duty cycle and period equal to the MVIP C2 signal. Frame Group A framing signals (Output). Programmable framing signals. The frame group outputs are determined by mode bits in the frame register to be either programmed outputs, output drive enables for DSo, or output framing pulses for use with local serial data streams. Description
FGB[0:11]
Frame Group B framing signals (Output). Programmable framing signals. The frame group outputs are determined by mode bits in the frame register to be either programmed outputs, output drive enables for DSi, or output framing pulses for use with local serial data streams.
RESET AD[0:7]
Chip Reset (Schmitt Input). This active low reset clears all internal registers, except connection memory and data memory. Microprocessor Address/Data Bus (Bidirectional TTL). Microprocessor access to internal registers, connection and data memories. In non-multiplexed mode: data bus. In multiplexed mode: multiplexed address and data bus. Microprocessor Address (TTL Input). In non-multiplexed mode: address to FMIC internal registers In multiplexed mode: unused (leave unconnected). Microprocessor Address Latch Enable (TTL Input). Selects the microprocessor mode. In Intel multiplexed mode, the falling edge of this signal is used to sample the address. Microprocessor Bus Chip Select (TTL Input). This active low input enables microprocessor access to connection and data memory and internal registers. Read/Data Strobe (TTL Input). In Intel mode (RD), this active low input configures the data bus lines as output. In Motorola mode (DS), this active low input operates with CS to enable read and write operation. Write\ Read/Write Strobe (TTL Input). In Intel mode (WR), this active low input configures the data bus lines as inputs. In Motorola mode (R/W), this input controls the direction of the data bus D[0:7] during a microprocessor access. Ready/Data Acknowledge (Open Drain Output). In Intel mode (RDY), this output acts as IOCHRDY. A 10K pull up is required. In Motorola mode (DTACK), this active low output indicates a successful data bus transfer. A 10K pull up is required.
A[0:1]
29
ALE
27 26
CS RD/[DS]
25
WR/[R/W]
30
RDY [DTACK]
2-171
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