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Details, datasheet, quote on part number:MT90820
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| Part: | MT90820 |
| Category: | Logic => Switches |
| Description: | 2048 X 2048 Channels Selectable Rate (2, 4, 8 Mbps) Non-blocking Large Digital Switch (LDX) |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT90820 datasheet File size : 630 kB |
| Request For quote: | Find where to buy MT90820
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Datasheet text preview:
CMOS ST-BUS FAMILY MT90820 Large Digital Switch
Features
· · · · · · · · · · · 2,048 × 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay Automatic identification of ST-BUS/GCI interfaces Accept ST-BUS streams of 2.048Mb/s, 4.096Mb/s or 8.192Mb/s Automatic frame offset delay measurement Per-stream frame delay offset programming Per-channel high impedance output control Per-channel message mode Control interface compatible to Motorola non-mulitplexed CPUs Connection memory block programming IEEE-1149.1 (JTAG) Test Port
DS5362
ISSUE 6
April 2000
Ordering Information MT90820AP MT90820AL 8 4 Pin PLCC 100 Pin MQFP
-40 to +85°C
Description
The MT90820 Large Digital Switch has a non-blocking switch capacity of 2,048 x 2,048 channels at a serial bit rate of 8.192Mb/s, 1,024 x 1,024 channels at 4.096Mb/s and 512 x 512 channels at 2.048Mb/s. The device has many features that are programmable on per stream or per channel basis, including message mode, input offset delay and high impedance output control. Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, input stream can be individually calibrated for input frame offset using a dedicated pin.
Applications
· · · · · · Medium and large switching platforms CTI application Voice/da t a multiplexer Digital cross connects ST-BUS/ G C I interface functions Suppor t IEEE 802.9a standard
VDD VSS TMS TDI TDO TCK
TRST
IC
RESET
ODE
Test Port STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15
Serial to Parallel Converter
Loopback Parallel Multiple Buffer Data Memory Output MUX to Serial Converter
Internal Registers
Connection Memory
Timing Unit
Microprocessor Interface
CLK
F0i
FE/ WFPS HCLK
AS/ IM DS/ CS R/W ALE RD /WR
A7-A0 DTA D15-D8/ CSTo AD7-AD0
Figure 1 - Functional Block Diagram
1
MT90820
CMOS
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 F0i FE/HCLK VSS CLK VDD
VSS STo15 STo14 STo13 STo12 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS
10 13 15 17 19 21 23 25 27 29 31 34 36 38 40 42 44 46 48 50 8 6 4 2 84 82 80 78 76 73 71 69 67
84 PIN PLCC
65 63 61 59 57 55 52
CSTo DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VSS
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 F0i FE/HCLK VSS CLK
80 82
NC NC NC NC VSS STo15 STo14 STo13 STo12 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS CSTo NC NC NC NC
78 76 74 72 70 68 66 64 62 60 58 56 54 52
TMS TDI TDO TCK TRST IC RESET WFPS A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W/RW CS AS/ALE IM
50 48
84 46 86 44 88 42 90 92 94 36 96 34 98 99 2 4 6 8 10 12 14 16 18 20 22 24 26 28 32 30 40 38
100 PIN MQFP
DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VSS
2
NC NC NC NC VDD TMS TDI TDO TCK TRST IC RESET WFPS A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W/RW CS AS/ALE IM NC NC NC NC
Figure 2 - Pin Connections
CMOS
Pin Description
Pin # 84 PLCC 1, 11, 30, 54 64, 75 2, 32, 63 3 - 10 100 MQFP 31, 41, 56, 66, 76, 99 5, 40, 67 68-75 Name Description
MT90820
VSS
Ground.
VDD STo8 - 15
+5 Volt Power Supply. ST-BUS Output 8 to 15 (Three-state Outputs): Serial data Output stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 - 1 in the IMS register. ST-BUS Input 0 to 15 (Inputs): Serial data input stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 - 1 in the IMS register. Frame Pulse (Input): When the WFPS pin is low, this input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI specifications. When the WFPS pin is high, this pin accepts a negative frame pulse which conforms to WFPS formats. Frame Evaluation / HCLK Clock (Input): When the WFPS pin is low, this pin is the frame measurement input. When the WFPS pin is high, the HCLK (4.096MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode. Clock (Input): Serial clock for shifting data in/out on the serial streams (STi/o 0 15). Depending upon the value programmed at bits DR0 - 1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock. Test Mode Select (Input): JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. Test Serial Data In (Input): JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. Test Serial Data Out (Output): JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enable. Test Clock (Input): Provides the clock to the JTAG test logic. This pin is pulled high by an internal pull-up when not driven. Test Reset (Input): Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed low on power-up, or held low, to ensure that the MT90820 is in the normal functional mode. Internal Connection (Input): Connect to VSS for normal operation. This pin must be low for the MT90820 to function normally and to comply with IEEE 1149 (JTAG) boundary scan requirements. This pin is pulled low internally when not driven. Device Reset (Schmitt Trigger Input): This input (active LOW) puts the MT90820 in its reset state that clears the device internal counters, registers and brings STo0 - 15 and microport data outputs to a high impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held low for a minimum of 100nsec to reset the device.
12 27 28
81-96
STi0 - 15
97
F0i
29
98
FE/HCLK
31
100
CLK
33 34 35
6 7 8
TMS TDI TDO
36 37
9 10
TCK TRST
38
11
IC
39
12
RESET
3
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